📄 viterbi_function.mdl
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IgnoreCustomStorageClasses on
IncHierarchyInIds off
MaxIdLength 31
PreserveName off
PreserveNameWithParent off
ShowEliminatedStatement off
IncAutoGenComments off
SimulinkDataObjDesc off
SFDataObjDesc off
IncDataTypeInIds off
PrefixModelToSubsysFcnNames on
CustomSymbolStr "$R$N$M"
MangleLength 1
DefineNamingRule "None"
ParamNamingRule "None"
SignalNamingRule "None"
InsertBlockDesc off
SimulinkBlockComments on
EnableCustomComments off
InlinedPrmAccess "Literals"
ReqsInCode off
}
Simulink.GRTTargetCC {
$BackupClass "Simulink.TargetCC"
$ObjectID 10
Array {
Type "Cell"
Dimension 12
Cell "IncludeMdlTerminateFcn"
Cell "CombineOutputUpdateFcns"
Cell "SuppressErrorStatus"
Cell "ERTCustomFileBanners"
Cell "GenerateSampleERTMain"
Cell "MultiInstanceERTCode"
Cell "PurelyIntegerCode"
Cell "SupportNonFinite"
Cell "SupportComplex"
Cell "SupportAbsoluteTime"
Cell "SupportContinuousTime"
Cell "SupportNonInlinedSFcns"
PropName "DisabledProps"
}
Version "1.0.4"
TargetFcnLib "ansi_tfl_tmw.mat"
GenFloatMathFcnCalls "ANSI_C"
UtilityFuncGeneration "Auto"
GenerateFullHeader on
GenerateSampleERTMain off
IsPILTarget off
ModelReferenceCompliant on
IncludeMdlTerminateFcn on
CombineOutputUpdateFcns off
SuppressErrorStatus off
IncludeFileDelimiter "Auto"
ERTCustomFileBanners off
SupportAbsoluteTime on
LogVarNameModifier "rt_"
MatFileLogging on
MultiInstanceERTCode off
SupportNonFinite on
SupportComplex on
PurelyIntegerCode off
SupportContinuousTime on
SupportNonInlinedSFcns on
ExtMode off
ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
}
PropName "Components"
}
}
PropName "Components"
}
Name "Configuration"
SimulationMode "normal"
CurrentDlgPage "Solver"
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Display
Format "short"
Decimation "10"
Floating off
SampleTime "-1"
}
Block {
BlockType Outport
Port "1"
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Reference
}
Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType "S-Function"
FunctionName "system"
PortCounts "[]"
SFunctionModules "''"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType ToWorkspace
VariableName "simulink_output"
MaxDataPoints "1000"
Decimation "1"
SampleTime "0"
FixptAsFi off
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "viterbi_function"
Location [2, 82, 1270, 753]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Display
Name "After Decode Display"
Ports [1]
Position [820, 154, 900, 356]
DropShadow on
Decimation "1"
}
Block {
BlockType Display
Name "Before Encode Display\n"
Ports [1]
Position [695, 154, 785, 356]
DropShadow on
Decimation "1"
}
Block {
BlockType Reference
Name "Bernoulli Binary\nGenerator"
Ports [0, 1]
Position [115, 293, 195, 337]
DropShadow on
FontName "Arial"
SourceBlock "commrandsrc2/Bernoulli Binary\nGenerator"
SourceType "Bernoulli Binary Generator"
ShowPortLabels on
P "0.5"
seed "435343"
Ts "0.0001"
frameBased on
sampPerFrame "10000"
orient off
}
Block {
BlockType Reference
Name "Convolutional\nEncoder"
Ports [1, 1]
Position [275, 285, 395, 345]
DropShadow on
SourceBlock "commcnvcod2/Convolutional\nEncoder"
SourceType "Convolutional Encoder"
trellis "poly2trellis(9, [753 561])"
reset "On each frame"
}
Block {
BlockType ToWorkspace
Name "To Workspace"
Position [615, 300, 675, 330]
DropShadow on
VariableName "output"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Structure"
}
Block {
BlockType ToWorkspace
Name "To Workspace1"
Position [475, 375, 535, 405]
DropShadow on
VariableName "Input"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Structure"
}
Block {
BlockType Reference
Name "Viterbi Decoder"
Ports [1, 1]
Position [445, 285, 565, 345]
DropShadow on
SourceBlock "commcnvcod2/Viterbi Decoder"
SourceType "Viterbi Decoder"
trellis "poly2trellis(9, [753 561])"
dectype "Hard Decision"
nsdecb "4"
tbdepth "96"
opmode "Truncated"
reset off
}
Line {
SrcBlock "Bernoulli Binary\nGenerator"
SrcPort 1
Points [0, 0; 30, 0]
Branch {
DstBlock "Convolutional\nEncoder"
DstPort 1
}
Branch {
Points [0, 75]
DstBlock "To Workspace1"
DstPort 1
}
Branch {
Points [0, -60]
DstBlock "Before Encode Display\n"
DstPort 1
}
}
Line {
SrcBlock "Convolutional\nEncoder"
SrcPort 1
DstBlock "Viterbi Decoder"
DstPort 1
}
Line {
SrcBlock "Viterbi Decoder"
SrcPort 1
Points [0, 0; 15, 0]
Branch {
DstBlock "To Workspace"
DstPort 1
}
Branch {
Points [0, 75; 215, 0; 0, -135]
DstBlock "After Decode Display"
DstPort 1
}
}
}
}
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