cc1100.c

无线收发模块cc1100的配置程序cc1100.h,io.h和发送、接收程序cc1100.c

//#include----------------------------------
#include <intrins.h>
#include <absacc.h>
#include <reg51.h>
#include "cc1100.h"
#include "io.h"


//cc1100 parameter---------------------------------------------------
// Chipcon
// Product = CC1100
// Chip version = F   (VERSION = 0x03)
// Crystal accuracy = 10 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 325.000000 kHz
// Deviation = 48 kHz
// Datarate = 99.975586 kBaud
// Modulation = (0) 2-FSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 432.999817 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = -
// Sync mode = (2) 16/16 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (0) FIX length packets
// Preamble count = (2)  4 bytes
// Append status = 0
// Addhress check = (0) No address check
// FIFO autoflush = 1
// Device address = 0
// GDO0 signal selection = (41) CHIP_RDY 
// GDO2 signal selection =(7) Asserts when a packet has been received deasserts when first byte is read from RX FIFO
const RF_SETTINGS rfSettings = {

//频率合成器控制1和0
    0x08,   //FSCTRL1   Frequency synthesizer control.
    0x00,   // FSCTRL0   Frequency synthesizer control.

//频率控制字，f_carrier=f_ref/2^16*freq[23:0] ,f_ref=26MHz
    0x10,   // FREQ2     Frequency control word, high byte.
    0xA7,   // FREQ1     Frequency control word, middle byte.
    0x62,   // FREQ0     Frequency control word, low byte.


//调制解调配置
    0x5B,   // MDMCFG4   Modem configuration. 信道滤波带宽配置
    0xF8,   // MDMCFG3   Modem configuration. 数据率配置
    0x02,   // MDMCFG2   Modem configuration. 调制方式配置，此时为2-FSK
    0x22,   // MDMCFG1   Modem configuration.
    0xF8,   // MDMCFG0   Modem configuration.
    0x00,   // CHANNR    Channel number.


    0x47,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).


    0xB6,   // FREND1    Front end RX configuration.
    0x10,   // FREND0    Front end RX configuration.
    0x27,   // MSSM1     RX complete ->FSTXON, TX complete -> RX


    0x18,   // MCSM0     Main Radio Control State Machine configuration.
    0x1D,   // FOCCFG    Frequency Offset Compensation Configuration.
    0x1C,   // BSCFG     Bit synchronization Configuration.
    0xC7,   // AGCCTRL2  AGC control.
    0x00,   // AGCCTRL1  AGC control.
    0xB2,   // AGCCTRL0  AGC control.
    0xEA,   // FSCAL3    Frequency synthesizer calibration.
    0x2A,   // FSCAL2    Frequency synthesizer calibration.
    0x00,   // FSCAL1    Frequency synthesizer calibration.
    0x1F,   // FSCAL0    Frequency synthesizer calibration.
    0x59,   // FSTEST    Frequency synthesizer calibration.
    0x81,   // TEST2     Various test settings.
    0x35,   // TEST1     Various test settings.
    0x09,   // TEST0     Various test settings.
    0x07,   // FIFOTHR   RXFIFO and TXFIFO thresholds.
    0x47,   // IOCFG2    GDO2 output pin configuration.
    0x48,   // IOCFG0D   GDO0 output pin configuration. 
    0x48,   // PKTCTRL1  Packet automation control.
    0x04,   // PKTCTRL0  Packet automation control.
    0x00,   // ADDR      Device address. 设备地址
    0x08    // PKTLEN    Packet length. 数据包长度
};

  
//P1.4--SO
//P1.5--SI
//P1.6--Csn
//P1.7--SCLK
//P3.2--GDO0
//P3.3--GDO2
void SpiWriteReg(byte address, byte value) {
  Csn=0;  
  InstructBit=address;
  SpiByte(0);
  InstructBit=value;
  SpiByte(0);
  
}

byte SpiReadReg(byte address) {
  Csn=0;
  address|=0x80;
  InstructBit=address;
  SpiByte(0);
  SpiByte(1);
  Csn=1; 
  return (ReadBit); 
  
}

void SpiCommandStrobe(byte address){
  Csn=0;
  InstructBit=address;
  SpiByte(0);
  Csn=1;
}
  

void SpiReadData(byte number) {
  byte i;
  
  Csn=0;

  InstructBit=RXBURST;    //burst access to RX FIFO
  SpiByte(0);
  for (i=0;i<number;i++) {
    SpiByte(1);
    receive[i]=ReadBit;
  }
  Csn=1;
}
  
    

void SpiWriteData(byte start, byte number) {
  byte i;
  
  Csn=0;
  InstructBit=TXBURST;   //burst access to TX FIFO
  SpiByte(0);
  for (i=start; i<=start+number-1;i++) {
    InstructBit=transmit[i];
    SpiByte(0);
  }
  Csn=1;
  
}
 
  
void SpiByte(byte r_w) {
  byte program_pointer=0;
  byte time_counter=0;
  byte temp;
  byte i;
 
  ReadBit=0;
  for (i=0; i<=50; i++)
  	_nop_();
  
  SCLK=0;
  
  while(program_pointer<=8) 
  {
    if (program_pointer==0) {
       if (r_w==0) {
 		    temp=InstructBit&0x80;
            SI=temp>>7;
			InstructBit=InstructBit<<1;
		 }
       else {
          ReadBit=ReadBit|SO;
		  ReadBit=ReadBit<<1;
		 }
       program_pointer++; 
    } 
    else {
      if (time_counter<=1) {
        SCLK =~SCLK; 
        time_counter++;
      }
      else if(time_counter==2) {
        time_counter++;
        
        if (program_pointer <8) {
          if (r_w==0) {
             temp=InstructBit&0x80;
          	 SI=temp>>7;
			    InstructBit=InstructBit<<1;
			 }
          
          else {
             ReadBit=ReadBit|SO;
			if (program_pointer<7) 
			    ReadBit=ReadBit<<1;
			}
                
        }
          
        
        program_pointer++;
      }
      else
        time_counter=0;  
    }
   
  }
   
}



void RfWriteRfSettings(void)
{
 // Write register settings
  Csn=0; 
  SpiWriteReg(FSCTRL1, rfSettings._FSCTRL1);
  SpiWriteReg(FSCTRL0, rfSettings._FSCTRL0);
  SpiWriteReg(FREQ2, rfSettings._FREQ2);
  SpiWriteReg(FREQ1, rfSettings._FREQ1);
  SpiWriteReg(FREQ0, rfSettings._FREQ0);
  SpiWriteReg(MDMCFG4, rfSettings._MDMCFG4);
  SpiWriteReg(MDMCFG3, rfSettings._MDMCFG3);
  SpiWriteReg(MDMCFG2, rfSettings._MDMCFG2);
  SpiWriteReg(MDMCFG1, rfSettings._MDMCFG1);
  SpiWriteReg(MDMCFG0, rfSettings._MDMCFG0);
  SpiWriteReg(CHANNR, rfSettings._CHANNR);
  SpiWriteReg(DEVIATN, rfSettings._DEVIATN);
  SpiWriteReg(FREND1, rfSettings._FREND1);
  SpiWriteReg(FREND0, rfSettings._FREND0);
  SpiWriteReg(MCSM1 , rfSettings._MCSM1 );
  SpiWriteReg(MCSM0 , rfSettings._MCSM0 );
  SpiWriteReg(FOCCFG, rfSettings._FOCCFG);
  SpiWriteReg(BSCFG, rfSettings._BSCFG);
  SpiWriteReg(AGCCTRL2, rfSettings._AGCCTRL2);
  SpiWriteReg(AGCCTRL1, rfSettings._AGCCTRL1);
  SpiWriteReg(AGCCTRL0, rfSettings._AGCCTRL0);
  SpiWriteReg(FSCAL3, rfSettings._FSCAL3);
  SpiWriteReg(FSCAL2, rfSettings._FSCAL2);
  SpiWriteReg(FSCAL1, rfSettings._FSCAL1);
  SpiWriteReg(FSCAL0, rfSettings._FSCAL0);
  SpiWriteReg(FSTEST, rfSettings._FSTEST);
  SpiWriteReg(TEST2, rfSettings._TEST2);
  SpiWriteReg(TEST1, rfSettings._TEST1);
  SpiWriteReg(TEST0, rfSettings._TEST0);
  SpiWriteReg(IOCFG2, rfSettings._IOCFG2);
  SpiWriteReg(IOCFG0, rfSettings._IOCFG0);
  SpiWriteReg(PKTCTRL1, rfSettings._PKTCTRL1);
  SpiWriteReg(PKTCTRL0, rfSettings._PKTCTRL0);
  SpiWriteReg(ADDR, rfSettings._ADDR);
  SpiWriteReg(PKTLEN, rfSettings._PKTLEN);
  Csn=1;
}