tcc79x_structures.h

自己在wince的环境下做的一移动数字电视驱动

	volatile unsigned int	CCIR656FCR2;				// 0x08 W/R 0x010b CCIR656 Format Configuration Register 2
	volatile unsigned int	IIS;					// 0x0C W/R 0x00000000 Input Image Size
	volatile unsigned int	IIW1;					// 0x10 W/R 0x00000000 Input Image Windowing 1
	volatile unsigned int	IIW2;					// 0x14 W/R 0x00000000 Input Image Windowing 2
	volatile unsigned int	CDCR1;					// 0x18 W/R 0x0003 DMA Configuration Register 1
	volatile unsigned int	CDCR2;					// 0x1C W/R 0x00000000 DMA Configuration Register 2
	volatile unsigned int	CDCR3;					// 0x20 W/R 0x00000000 DMA Configuration Register 3
	volatile unsigned int	CDCR4;					// 0x24 W/R 0x00000000 DMA Configuration Register 4
	volatile unsigned int	CDCR5;					// 0x28 W/R 0x00000000 DMA Configuration Register 5
	volatile unsigned int	CDCR6;					// 0x2C W/R 0x00000000 DMA Configuration Register 6
	volatile unsigned int	CDCR7;					// 0x30 W/R 0x00000000 DMA Configuration Register 7
	volatile unsigned int	FIFOSTATE;				// 0x34 R 0x00000000 FIFO Status Register
	volatile unsigned int	CIRQ;					// 0x38 W/R 0x00000000 Interrupt & Status register
	volatile unsigned int	OCTRL1;					// 0x3C W/R 0x37000000 Overlay Control 1
	volatile unsigned int	OCTRL2;					// 0x40 W/R 0x00000000 Overlay Control 2
	volatile unsigned int	OCTRL3;					// 0x44 W/R 0x00000000 Overlay Control 3
	volatile unsigned int	OCTRL4;					// 0x48 W/R 0x00000000 Overlay Control 4
	volatile unsigned int	OIS;					// 0x4C W/R 0x00000000 Overlay Image Size
	volatile unsigned int	OIW1;					// 0x50 W/R 0x00000000 Overlay Image Windowing 1
	volatile unsigned int	OIW2;					// 0x54 W/R 0x00000000 Overlay Image Windowing 2
	volatile unsigned int	COBA;					// 0x58 W/R 0x00000000 Overlay Base Address
	volatile unsigned int	CDS;					// 0x5C W/R 0x00000000 Camera Down Scaler
	volatile unsigned int	CCM1;					// 0x60 W/R 0x00000000 Capture Mode Configuration 1
	volatile unsigned int	CCM2;					// 0x64 W/R 0x00000000 Capture Mode Configuration 2
	volatile unsigned int	CESA;					// 0x68 W/R 0x00000000 Point Encoding Start Address
	volatile unsigned int	CR2Y;					// 0x6C W/R 0x00000000 RGB2YUV Format converter Configuration
	volatile unsigned int	CCYA;					// 0x70 R - Current Y Address
	volatile unsigned int	CCYU;					// 0x74 R - Current U Address
	volatile unsigned int	CCYV;					// 0x78 R - Current V Address
	volatile unsigned int	CCLC;					// 0x7C R Current Line count
}CIF, * PCIF;

//Effect Register Map (Base Address = 0xF0060100)
//#define HwEFFECT			0xF0060100
typedef struct _EFFECT{
	volatile unsigned int	EMR;					// 0x00 W/R 0x00000000 Effect mode register
	volatile unsigned int	SEPIAUV;				// 0x04 W/R 0x00000000 Sepia UV setting
	volatile unsigned int	CSR;					// 0x08 W/R 0x00000000 Color selection register
	volatile unsigned int	HFIL_COEF;				// 0x0C W/R 0x00000000 H-filter coefficent0
	volatile unsigned int	SKETCHTH;				// 0x10 W/R 0x00000000 Sketch threshold register
	volatile unsigned int	CLAMPTH;				// 0x14 W/R 0x00000000 Clamp threshold register
	volatile unsigned int	BIAS;					// 0x18 W/R 0x00000000 BIAS register
	volatile unsigned int	ISIZE;					// 0x1C W/R 0x00000000 Image size register
	volatile unsigned int	NOTDEFINE0[8];			// 0x20, 24, 28, 2C, 30, 34, 38, 3C,
	volatile unsigned int	INPATH_CTRL;			// 0x40 W/R 0x00000000 Inpath configuration
	volatile unsigned int	SRC_ADDRY;				// 0x44 W/R 0x00000000 Source address in Y channel
	volatile unsigned int	SRC_ADDRU;				// 0x48 W/R 0x00000000 Source address in U channel
	volatile unsigned int	SRC_ADDRV;				// 0x4C W/R 0x00000000 Source address in V channel
	volatile unsigned int	SRC_SIZE;				// 0x50 W/R 0x00000000 Source image size
	volatile unsigned int	SRC_OFFS;				// 0x54 W/R 0x00000000 Source image offset
	volatile unsigned int	DST_SIZE;				// 0x58 W/R 0x00000000 Destination image size
	volatile unsigned int	TAR_SCALE;				// 0x5C W/R 0x00000000 Target scale	
}EFFECT, * PEFFECT;

//Scaler Register Map (Base Address = 0xF0060200)
//#define HwCIFSACLER		0xF0060200
typedef struct _CIFSACLER{
	volatile unsigned int	SC_CTRL;				// 0x00 W/R 0x00000000 Scaler configuration
	volatile unsigned int	SC_SCALE;				// 0x04 W/R 0x00000000 Scale factor
	volatile unsigned int	SC_SRC_OFFSET;			// 0x08 W/R 0x00000000 Image offset
	volatile unsigned int	SC_SRC_SIZE;			// 0x0C W/R 0x00000000 Source image size
	volatile unsigned int	SC_DST_SIZE;			// 0x10 W/R 0x00000000 Destination image size
}CIFSACLER,* PCIFSACLER;

/************************************************************************
*	GRAPHIC ENGINE Definition
************************************************************************/
//Graphic Engine Register Map (Base Address = 0xF6000000)
//#define HwGE					0xF6000000
typedef struct _GE{
	volatile unsigned int	FCH0_SADDR0;		// 0x00 R/W 0x00000000 Front-End Channel 0 Source Address 0
	volatile unsigned int	FCH0_SADDR1;		// 0x04 R/W 0x00000000 Front-End Channel 0 Source Address 1
	volatile unsigned int	FCH0_SADDR2;		// 0x08 R/W 0x00000000 Front-End Channel 0 Source Address 2
	volatile unsigned int	FCH0_SFSIZE;		// 0x0C R/W 0x00000000 Front-End Channel 0 Source Frame Pixel Size
	volatile unsigned int	FCH0_SOFF;			// 0x10 R/W 0x00000000 Front-End Channel 0 Source Pixel Offset
	volatile unsigned int	FCH0_SISIZE;		// 0x14 R/W 0x00000000 Front-End Channel 0 Source Image Pixel Size
	volatile unsigned int	FCH0_WOFF;			// 0x18 R/W 0x00000000 Front-End Channel 0 Window Pixel Offset
	volatile unsigned int	FCH0_SCTRL;			// 0x1C R/W 0x00000000 Front-End Channel 0 Control
	volatile unsigned int	FCH1_SADDR0;		// 0x20 R/W 0x00000000 Front-End Channel 1 Source Address 0
	volatile unsigned int	FCH1_SADDR1;		// 0x24 R/W 0x00000000 Front-End Channel 1 Source Address 1
	volatile unsigned int	FCH1_SADDR2;		// 0x28 R/W 0x00000000 Front-End Channel 1 Source Address 2
	volatile unsigned int	FCH1_SFSIZE;		// 0x2C R/W 0x00000000 Front-End Channel 1 Source Frame Pixel Size
	volatile unsigned int	FCH1_SOFF;			// 0x30 R/W 0x00000000 Front-End Channel 1 Source Pixel Offset
	volatile unsigned int	FCH1_SISIZE;		// 0x34 R/W 0x00000000 Front-End Channel 1 Source Image Pixel Size
	volatile unsigned int	FCH1_WOFF;			// 0x38 R/W 0x00000000 Front-End Channel 1 Window Pixel Offset
	volatile unsigned int	FCH1_SCTRL;			// 0x3C R/W 0x00000000 Front-End Channel 1 Control
	volatile unsigned int	NOTDEFINE0[8];		// 0x40, 44, 48, 4C, 50, 54, 58, 5C
	volatile unsigned int	S0_CHROMA;			// 0x60 R/W 0x00000000 Source 0 Chroma-Key Parameter
	volatile unsigned int	S0_PAR;				// 0x64 R/W 0x00000000 Source 0 Arithmetic Parameter
	volatile unsigned int	S1_CHROMA;			// 0x68 R/W 0x00000000 Source 1 Chroma-Key Parameter
	volatile unsigned int	S1_PAR;				// 0x6C R/W 0x00000000 Source 1 Arithmetic Parameter
	volatile unsigned int	S2_CHROMA;			// 0x70 R/W 0x00000000 Source 2 Chroma-Key Parameter
	volatile unsigned int	S2_PAR;				// 0x74 R/W 0x00000000 Source 2 Arithmetic Parameter
	volatile unsigned int	S_CTRL;				// 0x78 R/W 0x00000000 Source Control Register
	volatile unsigned int	NOTDEFINE1;			//- 0x7C - - Reserved
	volatile unsigned int	OP0_PAT;			// 0x80 R/W 0x00000000 Source Operator 0 Pattern
	volatile unsigned int	OP1_PAT;			// 0x84 R/W 0x00000000 Source Operator 1 Pattern
	volatile unsigned int	OP_CTRL;			// 0x88 R/W 0x00000000 Source Operation Control Register
	volatile unsigned int	NOTDEFINE2;			//- 0x8C - - Reserved
	volatile unsigned int	BCH_DADDR0;			// 0x90 R/W 0x00000000 Back-End Channel Destination Address 0
	volatile unsigned int	BCH_DADDR1;			// 0x94 R/W 0x00000000 Back -End Channel Destination Address 1
	volatile unsigned int	BCH_DADDR2;			// 0x98 R/W 0x00000000 Back -End Channel Destination Address 2
	volatile unsigned int	BCH_DFSIZE;			// 0x9C R/W 0x00000000 Back -End Channel Destination Frame Pixel Size
	volatile unsigned int	BCH_DOFF;			// 0xA0 R/W 0x00000000 Back -End Channel Destination Pixel Offset
	volatile unsigned int	BCH_DCTRL;			// 0xA4 R/W 0x00000000 Back -End Channel Control
	volatile unsigned int	NOTDEFINE3[2];		// 0xA8, AC
	volatile unsigned int	GE_CTRL;			// 0xB0 R/W 0x00000000 Graphic Engine Control
	volatile unsigned int	GE_IREQ;			// 0xB4 R/W 0x00000000 Graphic Engine Interrupt Request
}GE, *PGE;

/************************************************************************
* EHI Definition
************************************************************************/
//The EHI registers are shown in Table 18.2. Chip Select 0 (HPCSN_L) base address is
//0xF5000000 and Chip Select 1 (HPCSN) 1 base address is 0xF00A0000.
//EHI register map
//#define HwEHICH0			0xF000000
//#define HwEHICH1			0xF00A000	
typedef struct _EHI{
	volatile unsigned int	EHST;					// 0x00 R/W R/W 0x00000080 Status register
	volatile unsigned int	EHIINT;					// 0x04 R/W R/W 0x00000000 Internal interrupt control register
	volatile unsigned int	EHEINT;					// 0x08 R/W R/W 0x00000000 External interrupt control register
	volatile unsigned int	EHA;					// 0x0C R R/W 0x00000000 Address register
	volatile unsigned int	EHAM ;					// 0x10 R/W R 0x00000000 Address masking register
	volatile unsigned int	EHD;					// 0x14 R/W R/W 0x00000000 Data register
	volatile unsigned int	EHSEM;					// 0x18 R/W R/W 0x00000000 Semaphore register
	volatile unsigned int	EHCFG;					// 0x1C R/W R/W 0x00000000 Configuration registers
	volatile unsigned int	EHIND;					// 0x20 R W 0x00000000 Index register
	volatile unsigned int	EHRWCS;					// 0x24 R R/W 0x00000000 Read/Write Control/Status register
}EHI,* PECHI;


/************************************************************************
*	DAI&CDIF Definition
************************************************************************/
//DAI Register Map (Base Address = 0xF0059000)
//#define HwDAI					0xF0059000
typedef struct _DAI{
	volatile unsigned int	DADI_L0;				// 0x00 R - Digital Audio Left Input Register 0
	volatile unsigned int	DADI_R0;				// 0x04 R - Digital Audio Right Input Register 0
	volatile unsigned int	DADI_L1;				// 0x08 R - Digital Audio Left Input Register 1
	volatile unsigned int	DADI_R1;				// 0x0C R - Digital Audio Right Input Register 1
	volatile unsigned int	DADI_L2;				// 0x10 R - Digital Audio Right Input Register 2
	volatile unsigned int	DADI_R2;				// 0x14 R - Digital Audio Right Input Register 2
	volatile unsigned int	DADI_L3;				// 0x18 R - Digital Audio Right Input Register 3
	volatile unsigned int	DADI_R3;				// 0x1C R - Digital Audio Right Input Register 3
	volatile unsigned int	DADO_L0;				// 0x20 R/W - Digital Audio Left Output Register 0
	volatile unsigned int	DADO_R0;				// 0x24 R/W - Digital Audio Right Output Register 0
	volatile unsigned int	DADO_L1;				// 0x28 R/W - Digital Audio Left Output Register 1
	volatile unsigned int	DADO_R1;				// 0x2C R/W - Digital Audio Right Output Register 1
	volatile unsigned int	DADO_L2;				// 0x30 R/W - Digital Audio Left Output Register 2
	volatile unsigned int	DADO_R2;				// 0x34 R/W - Digital Audio Right Output Register 2
	volatile unsigned int	DADO_L3;				// 0x38 R/W - Digital Audio Left Output Register 3
	volatile unsigned int	DADO_R3;				// 0x3C R/W - Digital Audio Right Output Register 3
	volatile unsigned int	DAMR;					// 0x40 R/W 0x00000000 Digital Audio Mode Register
	volatile unsigned int	DAVC;					// 0x44 R/W 0x0000 Digital Audio Volume Control Register
}DAI, *PDAI;
//CDIF Register Map (Base Address = 0xF0059080)
//#define HwCDIF				0xF0059080
typedef struct _CDIF{
	volatile unsigned int	CDDI_0;					// 0x80 R CD Digital Audio Input Register 0
	volatile unsigned int	CDDI_1;					// 0x84 R CD Digital Audio Input Register 1
	volatile unsigned int	CDDI_2;					// 0x88 R CD Digital Audio Input Register 2
	volatile unsigned int	CDDI_3;					// 0x8C R CD Digital Audio Input Register 3
	volatile unsigned int	CICR;						// 0x90 R/W 0x0000 CD Interface Control Register	
}CDIF, *PCDIF;

typedef struct _DAICDIF{
	volatile unsigned int	DADI_L0;				// 0x00 R - Digital Audio Left Input Register 0
	volatile unsigned int	DADI_R0;				// 0x04 R - Digital Audio Right Input Register 0
	volatile unsigned int	DADI_L1;				// 0x08 R - Digital Audio Left Input Register 1
	volatile unsigned int	DADI_R1;				// 0x0C R - Digital Audio Right Input Register 1
	volatile unsigned int	DADI_L2;				// 0x10 R - Digital Audio Right Input Register 2
	volatile unsigned int	DADI_R2;				// 0x14 R - Digital Audio Right Input Register 2
	volatile unsigned int	DADI_L3;				// 0x18 R - Digital Audio Right Input Register 3
	volatile unsigned int	DADI_R3;				// 0x1C R - Digital Audio Right Input Register 3
	volatile unsigned int	DADO_L0;				// 0x20 R/W - Digital Audio Left Output Register 0
	volatile unsigned int	DADO_R0;				// 0x24 R/W - Digital Audio Right Output Register 0
	volatile unsigned int	DADO_L1;				// 0x28 R/W - Digital Audio Left Output Register 1
	volatile unsigned int	DADO_R1;				// 0x2C R/W - Digital Audio Right Output Register 1
	volatile unsigned int	DADO_L2;				// 0x30 R/W - Digital Audio Left Output Register 2
	volatile unsigned int	DADO_R2;				// 0x34 R/W - Digital Audio Right Output Register 2
	volatile unsigned int	DADO_L3;				// 0x38 R/W - Digital Audio Left Output Register 3
	volatile unsi