📄 tcc79x_structures.h
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volatile unsigned int DPARAM1; // 0x44 R/W 0x00000000 Parameter of Destination Block
volatile unsigned int NOTDEFINE3; // 0x48
volatile unsigned int C_DADR1; // 0x4C R 0x00000000 Current Address of Destination Block
volatile unsigned int HCOUNT1; // 0x50 R/W 0x00000000 Initial and Current Hop count
volatile unsigned int CHCTRL1; // 0x54 R/W 0x00000000 Channel Control Register
volatile unsigned int RPTCTRL1; // 0x58 R/W 0x00000000 Repeat Control Register
volatile unsigned int EXTREQ1; // 0x5C R/W 0x00000000 External DMA Request register
volatile unsigned int ST_SADR2; // 0x60 R/W 0x00000000 Start Address of Source Block
volatile unsigned int SPARAM2; // 0x64 R/W 0x00000000 Parameter of Source Block
volatile unsigned int NOTDEFINE4; // 0x68
volatile unsigned int C_SADR2; // 0x6C R 0x00000000 Current Address of Source Block
volatile unsigned int ST_DADR2; // 0x70 R/W 0x00000000 Start Address of Destination Block
volatile unsigned int DPARAM2; // 0x74 R/W 0x00000000 Parameter of Destination Block
volatile unsigned int NOTDEFINE5; // 0x78
volatile unsigned int C_DADR2; // 0x7C R 0x00000000 Current Address of Destination Block
volatile unsigned int HCOUNT2; // 0x80 R/W 0x00000000 Initial and Current Hop count
volatile unsigned int CHCTRL2; // 0x84 R/W 0x00000000 Channel Control Register
volatile unsigned int RPTCTRL2; // 0x88 R/W 0x00000000 Repeat Control Register
volatile unsigned int EXTREQ2; // 0x8C R/W 0x00000000 External DMA Request register
volatile unsigned int CHCONFIG; // 0x90 R/W 0x00000000 Channel Configuration Register
}DMA,* pDMA;
/************************************************************************
* MEMORY STICK Definition
************************************************************************/
//MSHC Register Map (Base Address = 0xF0051000)
//#define HwMSHC 0xF0051000
typedef struct _MSHC{
volatile unsigned int COMMAND; // 0x00 R/W 0x00000000 Command Register
volatile unsigned int DATA; // 0x04 R/W Unknown Data Register
volatile unsigned int STATUS; // 0x08 R/W 0x00001020 Status Register
volatile unsigned int SYSTEM; // 0x0C R/W 0x00004455 System Control Register
}MSHC,* PMSHC;
/************************************************************************
* SD/MMC CONTROLLER Definition
************************************************************************/
/************************************************************************
* NFC Definition ( Nand Frash Controller)
************************************************************************/
//Nand Flash Controller Register Map (Base Address = 0xF00B0000)
//#define HwNFC 0xF00B0000
typedef struct _NFC {
volatile unsigned int NFC_CMD; // 0x00 W - Nand Flash Command Register
volatile unsigned int NFC_LADDR; // 0x04 W - Nand Flash Linear Address Register
volatile unsigned int NFC_BADDR; // 0x08 W - Nand Flash Block Address Register
volatile unsigned int NFC_SADDR; // 0x0C W - Nand Flash Signal Address Register
volatile unsigned int NFC_WDATA; // 0x1x R/W Unknown Nand Flash Word Data Register
volatile unsigned int NOTDEFINE0[3]; // 0x14, 18, 1C
volatile unsigned int NFC_LDATA; // 0x2x/3x R/W Unknown Nand Flash Linear Data Register
volatile unsigned int NOTDEFINE1[7]; // 0x24, 28, 2C, 30, 34, 38, 3C
volatile unsigned int NFC_SDATA; // 0x40 R/W Unknown Nand Flash Single Data Register
volatile unsigned int NOTDEFINE2[3]; // 0x44, 48, 4C
volatile unsigned int NFC_CTRL; // 0x50 R/W 0x03e08000 Nand Flash Control Register
volatile unsigned int NFC_PSTART; // 0x54 W - Nand Flash Program Start Register
volatile unsigned int NFC_RSTART; // 0x58 W - Nand Flash Read Start Register
volatile unsigned int NFC_DSIZE; // 0x5C R/W 0x0000ffff Nand Flash Data Size Register
volatile unsigned int NFC_IREQ; // 0x60 R/W 0x07000000 Nand Flash Interrupt Request Register
volatile unsigned int NFC_RST; // 0x64 W - Nand Flash Controller Reset Register
volatile unsigned int NFC_CTRL1; // 0x68 R/W 0x00000000 Nand Flash Control Register 1
volatile unsigned int NOTDEFINE3; // 0x6C
volatile unsigned int NFC_MDATA; // 0x7x R/W Unknown Nand Flash Multiple Data Register
}NFC, * PNFC;
/************************************************************************
* ECC Definition
************************************************************************/
//ECC Register Map (Base Address = 0xF005B000)
//#define HwECC 0xF005B000
typedef struct _ECCSLC{
volatile unsigned int ECC_CTRL; // 0x00 R/W 0x00000000 ECC Control Register
volatile unsigned int ECC_BASE; // 0x04 R/W 0x00000000 Base Address for ECC Calculation
volatile unsigned int ECC_MASK; // 0x08 R/W 0x00000000 Address mask for ECC area.
volatile unsigned int ECC_CLEAR; // 0x0C R/W ECC Clear
volatile unsigned int SECC_0; // 0x10 R/W 0x00000000 1st SLC ECC Code Register
volatile unsigned int SECC_1; // 0x14 R/W 0x00000000 2nd SLC ECC Code register
volatile unsigned int SECC_2; // 0x18 R/W 0x00000000 3rd SLC ECC Code Register
volatile unsigned int SECC_3; // 0x1C R/W 0x00000000 4th SLC ECC Code Register
volatile unsigned int SECC_4; // 0x20 R/W 0x00000000 5th SLC ECC Code Register
volatile unsigned int SECC_5; // 0x24 R/W 0x00000000 6th SLC ECC Code Register
volatile unsigned int SECC_6; // 0x28 R/W 0x00000000 7th SLC ECC Code Register
volatile unsigned int SECC_7; // 0x2C R/W 0x00000000 8th SLC ECC Code Register
volatile unsigned int SECC_8; // 0x30 R/W 0x00000000 9th SLC ECC Code Register
volatile unsigned int SECC_9; // 0x34 R/W 0x00000000 10th SLC ECC Code Register
volatile unsigned int SECC_10; // 0x38 R/W 0x00000000 11th SLC ECC Code Register
volatile unsigned int SECC_11; // 0x3C R/W 0x00000000 12th SLC ECC Code Register
volatile unsigned int SECC_12; // 0x40 R/W 0x00000000 13th SLC ECC Code Register
volatile unsigned int SECC_13; // 0x44 R/W 0x00000000 14th SLC ECC Code Register
volatile unsigned int SECC_14; // 0x48 R/W 0x00000000 15th SLC ECC Code Register
volatile unsigned int SECC_15; // 0x4C R/W 0x00000000 16th SLC ECC Code Register
volatile unsigned int SECC_EADDR0; // 0x50 R 0x00000000 SLC ECC Error Address Register0
volatile unsigned int SECC_EADDR1; // 0x54 R 0x00000000 SLC ECC Error Address Register1
volatile unsigned int SECC_EADDR2; // 0x58 R 0x00000000 SLC ECC Error Address Register2
volatile unsigned int SECC_EADDR3; // 0x5C R 0x00000000 SLC ECC Error Address Register3
volatile unsigned int SECC_EADDR4; // 0x60 R 0x00000000 SLC ECC Error Address Register4
volatile unsigned int SECC_EADDR5; // 0x64 R 0x00000000 SLC ECC Error Address Register5
volatile unsigned int SECC_EADDR6; // 0x68 R 0x00000000 SLC ECC Error Address Register6
volatile unsigned int SECC_EADDR7; // 0x6C R 0x00000000 SLC ECC Error Address Register7
volatile unsigned int SECC_EADDR8; // 0x70 R 0x00000000 SLC ECC Error Address Register8
volatile unsigned int SECC_EADDR9; // 0x74 R 0x00000000 SLC ECC Error Address Register9
volatile unsigned int SECC_EADDR10; // 0x78 R 0x00000000 SLC ECC Error Address Register10
volatile unsigned int SECC_EADDR11; // 0x7C R 0x00000000 SLC ECC Error Address Register11
volatile unsigned int SECC_EADDR12; // 0x80 R 0x00000000 SLC ECC Error Address Register12
volatile unsigned int SECC_EADDR13; // 0x84 R 0x00000000 SLC ECC Error Address Register13
volatile unsigned int SECC_EADDR14; // 0x88 R 0x00000000 SLC ECC Error Address Register14
volatile unsigned int SECC_EADDR15; // 0x8C R 0x00000000 SLC ECC Error Address Register15
volatile unsigned int ERRNUM; // 0x90 R 0x00000000 ECC Error Number
volatile unsigned int ECC_IREQ; // 0x94 R/W 0x00000000 ECC Interrupt Control Register
volatile unsigned int ECC_FSMSTATE; // 0x98 R 0x00000001 ECC FSM State Register
volatile unsigned int NOTDEFINE0[20]; // 0xA0, A4, A8, AC, B0, B4, B8, BC, C0, C4, C8, CC, D0, D4, D8, DC, E0, E4, E8, EC
volatile unsigned int ENCSEED; // 0xF0 W Test Mode Register
volatile unsigned int ENCMASK; // 0xF4 W Test Mode Register
volatile unsigned int ENCDATA; // 0xF8 R/W Test Mode Register
}ECCSLC,* PECCSLC;
typedef struct _ECCMLC4{
volatile unsigned int ECC_CTRL; // 0x00 R/W 0x00000000 ECC Control Register
volatile unsigned int ECC_BASE; // 0x04 R/W 0x00000000 Base Address for ECC Calculation
volatile unsigned int ECC_MASK; // 0x08 R/W 0x00000000 Address mask for ECC area.
volatile unsigned int ECC_CLEAR; // 0x0C R/W ECC Clear
volatile unsigned int MECC4_0; // 0x10 R/W 0x00000000 1st MLC ECC4 Code Register
volatile unsigned int MECC4_1; // 0x14 R/W 0x00000000 2nd MLC ECC4 Code Register
volatile unsigned int MECC4_2; // 0x18 R/W 0x00000000 3rd MLC ECC4 Code Register
volatile unsigned int MECC4_EADDR0; // 0x50 R 0x00000000 MLC ECC Error Address Register0
volatile unsigned int MECC4_EADDR1; // 0x54 R 0x00000000 MLC ECC Error Address Register1
volatile unsigned int MECC4_EADDR2; // 0x58 R 0x00000000 MLC ECC Error Address Register2
volatile unsigned int MECC4_EADDR3; // 0x5C R 0x00000000 MLC ECC Error Address Register3
volatile unsigned int MECC4_EDATA0; // 0x70 R 0x00000000 MLC ECC Error Data Register0
volatile unsigned int MECC4_EDATA1; // 0x74 R 0x00000000 MLC ECC Error Data Register1
volatile unsigned int MECC4_EDATA2; // 0x78 R 0x00000000 MLC ECC Error Data Register2
volatile unsigned int MECC4_EDATA3; // 0x7C R 0x00000000 MLC ECC Error Data Register3
volatile unsigned int ERRNUM; // 0x90 R 0x00000000 ECC Error Number
volatile unsigned int ECC_IREQ; // 0x94 R/W 0x00000000 ECC Interrupt Control Register
volatile unsigned int ECC_FSMSTATE; // 0x98 R 0x00000001 ECC FSM State Register
volatile unsigned int NOTDEFINE0[20]; // 0xA0, A4, A8, AC, B0, B4, B8, BC, C0, C4, C8, CC, D0, D4, D8, DC, E0, E4, E8, EC
volatile unsigned int ENCSEED; // 0xF0 W Test Mode Register
volatile unsigned int ENCMASK; // 0xF4 W Test Mode Register
volatile unsigned int ENCDATA; // 0xF8 R/W Test Mode Register
}ECCMLC4,* PECCMLC4;
typedef struct _ECCMLC8{
volatile unsigned int ECC_CTRL; // 0x00 R/W 0x00000000 ECC Control Register
volatile unsigned int ECC_BASE; // 0x04 R/W 0x00000000 Base Address for ECC Calculation
volatile unsigned int ECC_MASK; // 0x08 R/W 0x00000000 Address mask for ECC area.
volatile unsigned int ECC_CLEAR; // 0x0C R/W ECC Clear
volatile unsigned int MECC8_0; // 0x10 R/W 0x00000000 1st MLC ECC8 Code Register
volatile unsigned int MECC8_1; // 0x14 R/W 0x00000000 2nd MLC ECC8 Code Register
volatile unsigned int MECC8_2; // 0x18 R/W 0x00000000 3rd MLC ECC8 Code Register
volatile unsigned int MECC8_3; // 0x1C R/W 0x00000000 4th MLC ECC8 Code Register
volatile unsigned int MECC8_4; // 0x20 R/W 0x00000000 5th MLC ECC8 Code Register
volatile unsigned int MECC8_EADDR0; // 0x50 R 0x00000000 MLC ECC8 Error Address Register0
volatile unsigned int MECC8_EADDR1; // 0x54 R 0x00000000 MLC ECC8 Error Address Register1
volatile unsigned int MECC8_EADDR2; // 0x58 R 0x00000000 MLC ECC8 Error Address Register2
volatile unsigned int MECC8_EADDR3; // 0x5C R 0x00000000 MLC ECC8 Error Address Register3
volatile unsigned int MECC8_EADDR4; // 0x60 R 0x00000000 MLC ECC8 Error Address Register4
volatile unsigned int MECC8_EADDR5; // 0x64 R 0x00000000 MLC ECC8 Error Address Register5
volatile unsigned int MECC8_EADDR6; // 0x68 R 0x00000000 MLC ECC8 Error Address Register6
volatile unsigned int MECC8_EADDR7; // 0x6C R 0x00000000 MLC ECC8 Error Address Register7
volatile unsigned int MECC8_EDATA0; // 0x70 R 0x00000000 MLC ECC8 Error Data Register0
volatile unsigned int MECC8_EDATA1; // 0x74 R 0x00000000 MLC ECC8 Error Data Register1
volatile unsigned int MECC8_EDATA2; // 0x78 R 0x00000000 MLC ECC8 Error Data Register2
volatile unsigned int MECC8_EDATA3; // 0x7C R 0x00000000 MLC ECC8 Error Data Register3
volatile unsigned int MECC8_EDATA4; // 0x80 R 0x00000000 MLC ECC8 Error Data Register4
volatile unsigned int MECC8_EDATA5; // 0x84 R 0x00000000 MLC ECC8 Error Data Register5
volatile unsigned int MECC8_EDATA6; // 0x88 R 0x00000000 MLC ECC8 Error Data Register6
volatile unsigned int MECC8_EDATA7; // 0x8C R 0x00000000 MLC ECC8 Error Data Register7
volatile unsigned int ERRNUM; // 0x90 R 0x00000000 ECC Error Number
volatile unsigned int ECC_IREQ; // 0x94 R/W 0x00000000 ECC Interrupt Control Register
volatile unsigned int ECC_FSMSTATE; // 0x98 R 0x00000001 ECC FSM State Register
volatile unsigned int NOTDEFINE0[20]; // 0xA0, A4, A8, AC, B0, B4, B8, BC, C0, C4, C8, CC, D0, D4, D8, DC, E0, E4, E8, EC
volatile unsigned int ENCSEED; // 0xF0 W Test Mode Register
volatile unsigned int ENCMASK; // 0xF4 W Test Mode Register
volatile unsigned int ENCDATA; // 0xF8 R/W Test Mode Register
}ECCMLC8,* PECCMLC8;
/************************************************************************
* CAMERA INTERFACE Definition
************************************************************************/
//CIF Register Map (Base Address = 0xF0060000)
//#define HwCIF 0xF0060000
typedef struct _CIF{
volatile unsigned int ICPCR1; // 0x00 W/R 0x00000000 Input Image Color/Pattern Configuration Register 1
volatile unsigned int CCIR656FCR1; // 0x04 W/R 0x06ff0000 CCIR656 Format Configuration Register 1
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