tcc79x_structures.h

自己在wince的环境下做的一移动数字电视驱动

	volatile unsigned int	DST_OFFSET;			// 0x030 R/W 0x00000000 Destination image line offset register
	volatile unsigned int	DST_CONFIG;			// 0x034 R/W 0x00000000 Destination image configuration register
	volatile unsigned int	NOTDEFINE1[2];		// 0x038, 3C
	volatile unsigned int	SCALE_RATIO;		// 0x040 R/W 0x00000000 Scale ratio register
	volatile unsigned int	SCALE_CTRL;			// 0x044 R/W 0x00000000 Scaler control register
	volatile unsigned int	STATUS;				// 0x048 R 0x00000000 Scaler status register
}SCALER,* PSCALER;

/************************************************************************
*	USB CONTROLLER Definition
************************************************************************/
//USB Register Map (Base Address = 0xF0010000)
//#define HwUSB					0xF0010000
typedef struct _USB {
	volatile unsigned int	IR;						//Index Register IR 0x00 
	volatile unsigned int	EIR;					//Endpoint Interrupt Register EIR 0x04 
	volatile unsigned int	EIER;					//Endpoint Interrupt Register EIER 0x08 
	volatile unsigned int	NOTDEFINE0;				//0x0C
	volatile unsigned int	EDR;					//Endpoint Direction Register EDR 0x14 
	volatile unsigned int	NOTDEFINE1;				//0x18 
	volatile unsigned int	SSR;					//System Status Register SSR 0x1C 
	volatile unsigned int	SCR;					//System Control Register SCR 0x20 
	volatile unsigned int	EP0SR;					//EP0 Status Register EP0SR 0x24 
	volatile unsigned int	EP0CR;					//EP0 Control Register EP0CR 0x28 
	volatile unsigned int	ESR;					//Endpoints Status Register ESR 0x2C
	volatile unsigned int	ECR;					//Endpoint Control Register ECR 0x30
	volatile unsigned int	BRCR;					//Byte Read Count Register BRCR 0x34
	volatile unsigned int	BWCR;					//Byte Write Count Register BWCR 0x38
	volatile unsigned int	MPR;					//Reserved Max Packet Register MPR 0x3C
	volatile unsigned int	DCR;					//DMA Control Register DCR 0x40
	volatile unsigned int	DTCR;					//DMA Transfer Counter Register DTCR 0x44
	volatile unsigned int	DFCR;					//DMA FIFO Counter Register DFCR 0x48
	volatile unsigned int	DTTCR1;					//DMA Total Transfer Counter1 Register DTTCR1 0x4C
	volatile unsigned int	DTTCR2;					//DMA Total Transfer Counter2 Register DTTCR2 0x50
	volatile unsigned int	NOTDEFINE2[3];			//0x54, 0x58, 0x5C
	volatile unsigned int	EP0BUF;					//EP0 Buffer Register EP0BUF 0x60
	volatile unsigned int	EP1BUF;					//EP1 Buffer Register EP1BUF 0x64
	volatile unsigned int	EP2BUF;					//EP2 Buffer Register EP2 BUF 0x68
	volatile unsigned int	EP3BUF;					//EP3 Buffer Register EP3 BUF 0x6C
	volatile unsigned int	NOTDEFINE3[12];	// 12[4 * 3(7,8,9)] 
	volatile unsigned int	DMAR1;					// 0xA0
	volatile unsigned int	DMAR2;					// 0xA4
	volatile unsigned int	NOTDEFINE4[6];	// [A8, AC, C0 + 4 * 1(B) +] 
	volatile unsigned int	UBCFG;					// C4
}USB, *pUSB;

//USB Host Register Map (Base Address = 0xF0020000)
//#define HwUSBHOST			0xF0020000
typedef struct _USBHOST{
	volatile unsigned int	HcRevision;				// 0x00 R 0x00000010
	volatile unsigned int	HcControl;				// 0x04 R/W 0x00000000
	volatile unsigned int	HcCommandStatus;		// 0x08 R 0x00000000
	volatile unsigned int	HcInterruptStatus;		// 0x0C R 0x00000000
	volatile unsigned int	HcInterruptEnable;		// 0x10 R/W 0x00000000
	volatile unsigned int	HcInterruptDisable;		// 0x14 W 0x00000000
	volatile unsigned int	HcHCCA;					// 0x18 R/W 0x00000000
	volatile unsigned int	HcPeriodCurrentED;		// 0x1C R 0x00000000
	volatile unsigned int	HcControlHeadED;		// 0x20 R/W 0x00000000
	volatile unsigned int	HcControlCurrentED;		// 0x24 R/W 0x00000000
	volatile unsigned int	HcBulkHeadED;			// 0x28 R/W 0x00000000
	volatile unsigned int	HcBulkCurrentED;		// 0x2C R/W 0x00000000
	volatile unsigned int	HcDoneHead;				// 0x30 R 0x00000000
	volatile unsigned int	HcRmInterval;			// 0x34 R/W 0x00002EDF
	volatile unsigned int	HcFmRemaining;			// 0x38 R/W 0x00000000
	volatile unsigned int	HcFmNumber;				// 0x3C R/W 0x00000000
	volatile unsigned int	HcPeriodStart;			// 0x40 R/W 0x00000000
	volatile unsigned int	HcLSThreshold;			// 0x44 R/W 0x00000628
	volatile unsigned int	HcRhDescriptorA;		// 0x48 R/W 0x02001202
	volatile unsigned int	HcRhDescriptorB;		// 0x4C R/W 0x00000000
	volatile unsigned int	HcRhStatus;				// 0x50 R/W 0x00000000
	volatile unsigned int	HcRhPortStatus1;		// 0x54 R/W 0x00000100
	volatile unsigned int	HcRhPortStatus2;		// 0x58 R/W 0x00000100
}USBHOST, * PUSBHOST;

/************************************************************************
*	IDE Definition
************************************************************************/
//IDE Registers (Base = 0xF0030000)
//#define HwIDE					0xF0030000
typedef struct _IDE{
	volatile unsigned int	CS000;					// 0x00~ 0x03 R/W - PIO CS0n Access Register
	volatile unsigned int	CS004;					// 0x04~ 0x07 R/W - PIO CS0n Access Register
	volatile unsigned int	CS008;					// 0x08~ 0x0B R/W - PIO CS0n Access Register
	volatile unsigned int	CS00C;					// 0x0C~ 0x0F R/W - PIO CS0n Access Register
	volatile unsigned int	CS010;					// 0x10~ 0x13 R/W - PIO CS0n Access Register
	volatile unsigned int	CS014;					// 0x14~ 0x17 R/W - PIO CS0n Access Register
	volatile unsigned int	CS018;					// 0x18~ 0x1B R/W - PIO CS0n Access Register
	volatile unsigned int	CS01C;					// 0x1C~ 0x1F R/W - PIO CS0n Access Register
	volatile unsigned int	CS120;					// 0x20~ 0x23 R/W - PIO CS1n Access Register
	volatile unsigned int	CS124;					// 0x24~ 0x27 R/W - PIO CS1n Access Register
	volatile unsigned int	CS128;					// 0x28~ 0x2B R/W - PIO CS1n Access Register
	volatile unsigned int	CS12C;					// 0x2C~ 0x2F R/W - PIO CS1n Access Register
	volatile unsigned int	CS130;					// 0x30~ 0x33 R/W - PIO CS1n Access Register
	volatile unsigned int	CS134;					// 0x34~ 0x37 R/W - PIO CS1n Access Register
	volatile unsigned int	CS138;					// 0x38~ 0x3B R/W - PIO CS1n Access Register
	volatile unsigned int	CS13C;					// 0x3C~ 0x3F R/W - PIO CS1n Access Register
	volatile unsigned int	PIOCTRL;				// 0x40 R/W 0x00600000 PIO Mode Control Register
	volatile unsigned int	UDMACTRL;				// 0x44 R/W 0x00000000 UDMA Mode Control Register
	volatile unsigned int	IDMACTRL;				// 0x48 R/W 0x00000000 IDMA Control Register
	volatile unsigned int	IDMASA;					// 0x4C R/W 0x00000000 IDMA Source Address Register
	volatile unsigned int	IDMASP;					// 0x50 R/W 0x00000000 IDMA Source Parameter Register
	volatile unsigned int	IDMACSA;				// 0x54 R 0x00000000 IDMA Current Source Address Register
	volatile unsigned int	IDMADA;					// 0x58 R/W 0x00000000 IDMA Destination Address Register
	volatile unsigned int	IDMADP;					// 0x5C R/W 0x00000000 IDMA Destination Parameter Register
	volatile unsigned int	IDMACDA;				// 0x60 R 0x00000000 IDMA Current Destination Address Register
	volatile unsigned int	IDEINT;					// 0x64 R/W 0x0000_0000 IDE Interrupt Register
	volatile unsigned int	UDMATCNT;				// 0x68 R/W 0x00FF_FFFF UDMA Transfer Counter Register
	volatile unsigned int	UDMAIN;					// 0x6C R - UDMA-IN Access Register
	volatile unsigned int	UDMAOUT;				// 0x70 W - UDMA-OUT Access register
	volatile unsigned int	UDMACRC;				// 0x74 R 0x0000_4ABA UDMA CRC Register
	volatile unsigned int	UDMACTCNT;				// 0x78 R 0x00FF_FFFF UDMA Current Transfer Counter Register
}IDE, * PIDE;

/************************************************************************
*	DMA CONTROLLER Definition
************************************************************************/
//General DMA0 Controller Register Map (Base Address = 0xF0040000)
//#define HwDMA0				0xF0040000
typedef struct _DMA0{
	volatile unsigned int	ST_SADR0;				// 0x00 R/W 0x00000000 Start Address of Source Block
	volatile unsigned int	SPARAM0;				// 0x04 R/W 0x00000000 Parameter of Source Block
	volatile unsigned int	NOTDEFINE0;				// 0x08
	volatile unsigned int	C_SADR0;				// 0x0C R 0x00000000 Current Address of Source Block
	volatile unsigned int	ST_DADR0;				// 0x10 R/W 0x00000000 Start Address of Destination Block
	volatile unsigned int	DPARAM0;				// 0x14 R/W 0x00000000 Parameter of Destination Block
	volatile unsigned int	NOTDEFINE1;				// 0x18
	volatile unsigned int	C_DADR0;				// 0x1C R 0x00000000 Current Address of Destination Block
	volatile unsigned int	HCOUNT0;				// 0x20 R/W 0x00000000 Initial and Current Hop count
	volatile unsigned int	CHCTRL0;				// 0x24 R/W 0x00000000 Channel Control Register
	volatile unsigned int	RPTCTRL0;				// 0x28 R/W 0x00000000 Repeat Control Register
	volatile unsigned int	EXTREQ0;				// 0x2C R/W 0x00000000 External DMA Request register
}DMA0,* pDMA0;

//General DMA1 Controller Register Map (Base Address = 0xF0040100)
//#define HwDMA1				0xF0040100
typedef struct _DMA1{
	volatile unsigned int	ST_SADR1;				// 0x30 R/W 0x00000000 Start Address of Source Block
	volatile unsigned int	SPARAM1;				// 0x34 R/W 0x00000000 Parameter of Source Block
	volatile unsigned int	NOTDEFINE0;				// 0x38
	volatile unsigned int	C_SADR1;				// 0x3C R 0x00000000 Current Address of Source Block
	volatile unsigned int	ST_DADR1;				// 0x40 R/W 0x00000000 Start Address of Destination Block
	volatile unsigned int	DPARAM1;				// 0x44 R/W 0x00000000 Parameter of Destination Block
	volatile unsigned int	NOTDEFINE1;				// 0x48
	volatile unsigned int	C_DADR1;				// 0x4C R 0x00000000 Current Address of Destination Block
	volatile unsigned int	HCOUNT1;				// 0x50 R/W 0x00000000 Initial and Current Hop count
	volatile unsigned int	CHCTRL1;				// 0x54 R/W 0x00000000 Channel Control Register
	volatile unsigned int	RPTCTRL1;				// 0x58 R/W 0x00000000 Repeat Control Register
	volatile unsigned int	EXTREQ1;				// 0x5C R/W 0x00000000 External DMA Request register
}DMA1,* pDMA1;

//General DMA2 Controller Register Map (Base Address = 0xF0040200)
//#define HwDMA2				0xF0040200
typedef struct _DMA2{
	volatile unsigned int	ST_SADR2;				// 0x60 R/W 0x00000000 Start Address of Source Block
	volatile unsigned int	SPARAM2;				// 0x64 R/W 0x00000000 Parameter of Source Block
	volatile unsigned int	NOTDEFINE0;				// 0x68
	volatile unsigned int	C_SADR2;				// 0x6C R 0x00000000 Current Address of Source Block
	volatile unsigned int	ST_DADR2;				// 0x70 R/W 0x00000000 Start Address of Destination Block
	volatile unsigned int	DPARAM2;				// 0x74 R/W 0x00000000 Parameter of Destination Block
	volatile unsigned int	NOTDEFINE1;				// 0x78
	volatile unsigned int	C_DADR2;				// 0x7C R 0x00000000 Current Address of Destination Block
	volatile unsigned int	HCOUNT2;				// 0x80 R/W 0x00000000 Initial and Current Hop count
	volatile unsigned int	CHCTRL2;				// 0x84 R/W 0x00000000 Channel Control Register
	volatile unsigned int	RPTCTRL2;				// 0x88 R/W 0x00000000 Repeat Control Register
	volatile unsigned int	EXTREQ2;				// 0x8C R/W 0x00000000 External DMA Request register
	volatile unsigned int	CHCONFIG;				// 0x90 R/W 0x00000000 Channel Configuration Register
}DMA2,* pDMA2;

typedef struct _DMA{
	volatile unsigned int	ST_SADR0;				// 0x00 R/W 0x00000000 Start Address of Source Block
	volatile unsigned int	SPARAM0;				// 0x04 R/W 0x00000000 Parameter of Source Block
	volatile unsigned int	NOTDEFINE0;				// 0x08
	volatile unsigned int	C_SADR0;				// 0x0C R 0x00000000 Current Address of Source Block
	volatile unsigned int	ST_DADR0;				// 0x10 R/W 0x00000000 Start Address of Destination Block
	volatile unsigned int	DPARAM0;				// 0x14 R/W 0x00000000 Parameter of Destination Block
	volatile unsigned int	NOTDEFINE1;				// 0x18
	volatile unsigned int	C_DADR0;				// 0x1C R 0x00000000 Current Address of Destination Block
	volatile unsigned int	HCOUNT0;				// 0x20 R/W 0x00000000 Initial and Current Hop count
	volatile unsigned int	CHCTRL0;				// 0x24 R/W 0x00000000 Channel Control Register
	volatile unsigned int	RPTCTRL0;				// 0x28 R/W 0x00000000 Repeat Control Register
	volatile unsigned int	EXTREQ0;				// 0x2C R/W 0x00000000 External DMA Request register
	volatile unsigned int	ST_SADR1;				// 0x30 R/W 0x00000000 Start Address of Source Block
	volatile unsigned int	SPARAM1;				// 0x34 R/W 0x00000000 Parameter of Source Block
	volatile unsigned int	NOTDEFINE2;				// 0x38
	volatile unsigned int	C_SADR1;				// 0x3C R 0x00000000 Current Address of Source Block
	volatile unsigned int	ST_DADR1;				// 0x40 R/W 0x00000000 Start Address of Destination Block