📄 tcc79x_structures.h
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#define HwPORTCFG4_GPIOA2(X) ((X)*Hw16) // GPIOA[2] = GPIOA[2] | CLK_OUT0 | - | - | - | -
#define HwPORTCFG4_GPIOA3(X) ((X)*Hw12) // GPIOA[3] = GPIOA[3] | CLK_OUT1 | - | - | - | -
#define HwPORTCFG4_GPIOA4(X) ((X)*Hw8) // GPIOA[4]* = GPIOA[4] | WDTRSTO | TCO3 | - | - | -
#define HwPORTCFG4_GPIOA5(X) ((X)*Hw4) // GPIOA[5]* = GPIOA[5] | - | TCO2 | - | - | -
#define HwPORTCFG4_CSN_CS0(X) ((X)*Hw0) // CSN_CS0 = CSN_CS0 | GPIOC[24] | - | - | - | -
#define HwPORTCFG5 *(volatile unsigned long *)0xF005A014 // R/W, Port Configuration Register 5
#define HwPORTCFG5_CSN_NOR(X) ((X)*Hw28) // CSN_NOR = CSN_NOR | GPIOF[28] | - | - | - | -
#define HwPORTCFG5_GPIOB0(X) ((X)*Hw24) // GPIOB[0] = GPIOB[0] | NDXD[0] | SD_D0(5) | SFRM(3) | - | SRAMIF_XD[0]
#define HwPORTCFG5_GPIOB1(X) ((X)*Hw20) // GPIOB[1] = GPIOB[1] | NDXD[1] | SD_D1(5) | SCLK(3) | - | SRAMIF_XD[1]
#define HwPORTCFG5_GPIOB2(X) ((X)*Hw16) // GPIOB[2] = GPIOB[2] | NDXD[2] | SD_D2(5) | SDI(3) | - | SRAMIF_XD[2]
#define HwPORTCFG5_GPIOB3(X) ((X)*Hw12) // GPIOB[3] = GPIOB[3] | NDXD[3] | SD_D3(5) | SDO(3) | - | SRAMIF_XD[3]
#define HwPORTCFG5_GPIOB4(X) ((X)*Hw8) // GPIOB[4] = GPIOB[4] | NDXD[4] | SD_D4(5) | SFRM(2) | - | SRAMIF_XD[4]
#define HwPORTCFG5_GPIOB5(X) ((X)*Hw4) // GPIOB[5] = GPIOB[5] | NDXD[5] | SD_D5(5) | SCLK(2) | - | SRAMIF_XD[5]
#define HwPORTCFG5_GPIOB6(X) ((X)*Hw0) // GPIOB[6] = GPIOB[6] | NDXD[6] | SD_D6(5) | SDI(2) | - | SRAMIF_XD[6]
#define HwPORTCFG6 *(volatile unsigned long *)0xF005A018 // R/W, Port Configuration Register 6
#define HwPORTCFG6_GPIOB7(X) ((X)*Hw28) // GPIOB[7] = GPIOB[7] | NDXD[7] | SD_D7(5) | SDO(2) | - | SRAMIF_XD[7]
#define HwPORTCFG6_GPIOB8(X) ((X)*Hw24) // GPIOB[8] = GPIOB[8] | NDOEN | SD_CMD(5) | - | - | SRAMIF_OEN
#define HwPORTCFG6_GPIOB9(X) ((X)*Hw20) // GPIOB[9] = GPIOB[9] | NDWEN | SD_CLK(5) | - | - | SRAMIF_WEN
#define HwPORTCFG6_GPIOB10(X) ((X)*Hw16) // GPIOB[10] = GPIOB[10] | NDCSN0 | SD_D0(6) | MS_D0(3) | SFRM(1) | SRAMIF_CSN0
#define HwPORTCFG6_GPIOB11(X) ((X)*Hw12) // GPIOB[11] = GPIOB[11] | NDCSN1 | SD_D1(6) | MS_D1(3) | SCLK(1) | SRAMIF_CSN1
#define HwPORTCFG6_GPIOB12(X) ((X)*Hw8) // GPIOB[12] = GPIOB[12] | NDCLE | SD_D2(6) | MS_D2(3) | SDI(1) | SRAMIF_XA[0]
#define HwPORTCFG6_GPIOB13(X) ((X)*Hw4) // GPIOB[13] = GPIOB[13] | NDALE | SD_D3(6) | MS_D3(3) | SDO(1) | SRAMIF_XA[1]
#define HwPORTCFG6_GPIOB14(X) ((X)*Hw0) // GPIOB[14] = GPIOB[14] | NDRDY0 | SD_CMD(6) | MS_BUS(3) | - | -
#define HwPORTCFG7 *(volatile unsigned long *)0xF005A01C // R/W, Port Configuration Register 7
#define HwPORTCFG7_GPIOB15(X) ((X)*Hw28) // GPIOB[15] = GPIOB[15] | NDRDY1 | SD_CLK(6) | MS_CLK(3) | - | -
#define HwPORTCFG7_SCMD1(X) ((X)*Hw24) // SCMD1 = SFRM(5) | GPIOD[9] | - | - | - | -
#define HwPORTCFG7_SCLK1(X) ((X)*Hw20) // SCLK1 = SCLK(5) | GPIOD[10] | - | - | - | -
#define HwPORTCFG7_SDI1(X) ((X)*Hw16) // SDI1 = SDI(5) | GPIOD[11] | - | - | - | -
#define HwPORTCFG7_SDO1(X) ((X)*Hw12) // SDO1 = SDO(5) | GPIOD[12] | - | - | - | -
#define HwPORTCFG7_GPIOA6(X) ((X)*Hw8) // GPIOA[6] = GPIOA[6] | SPDIFTX | TCO1 | - | - | -
#define HwPORTCFG7_GPIOA7(X) ((X)*Hw4) // GPIOA[7] = GPIOA[7] | EXTCLKI | TCO0 | - | - | -
#define HwPORTCFG7_GPIOA8(X) ((X)*Hw0) // GPIOA[8] = GPIOA[8] | SCL1 | - | - | - | -
#define HwPORTCFG8 *(volatile unsigned long *)0xF005A020 // R/W, Port Configuration Register 8
#define HwPORTCFG8_GPIOA9(X) ((X)*Hw28) // GPIOA[9] = GPIOA[9] | SDA1 | - | - | - | -
#define HwPORTCFG8_GPIOA10(X) ((X)*Hw24) // GPIOA[10] = GPIOA[10] | CBCLK | - | - | - | -
#define HwPORTCFG8_GPIOA11(X) ((X)*Hw20) // GPIOA[11] = GPIOA[11] | CLRCK | - | - | - | -
#define HwPORTCFG8_GPIOA12(X) ((X)*Hw16) // GPIOA[12] = GPIOA[12] | CDATA | - | - | - | -
#define HwPORTCFG8_AIN0(X) ((X)*Hw12) // AIN[0] = AIN[0] | GPIOE[24] | - | - | - | -
#define HwPORTCFG8_AIN1(X) ((X)*Hw8) // AIN[1] = AIN[1] | GPIOE[25] | - | - | - | -
#define HwPORTCFG8_AIN2(X) ((X)*Hw4) // AIN[2] = AIN[2] | GPIOE[26] | SD_CMD(7) | MS_BUS(4) | - | -
#define HwPORTCFG8_AIN3(X) ((X)*Hw0) // AIN[3] = AIN[3] | GPIOE[27] | SD_CLK(7) | MS_CLK(4) | - | -
#define HwPORTCFG9 *(volatile unsigned long *)0xF005A024 // R/W, Port Configuration Register 9
#define HwPORTCFG9_AIN4(X) ((X)*Hw28) // AIN[4] = AIN[4] | GPIOE[28] | SD_D0(7) | MS_D0(4) | SFRM(0) | -
#define HwPORTCFG9_AIN5(X) ((X)*Hw24) // AIN[5] = AIN[5] | GPIOE[29] | SD_D1(7) | MS_D1(4) | SCLK(0) | -
#define HwPORTCFG9_AIN6(X) ((X)*Hw20) // AIN[6] = AIN[6] | GPIOE[30] | SD_D2(7) | MS_D2(4) | SDI(0) | -
#define HwPORTCFG9_AIN7(X) ((X)*Hw16) // AIN[7] = AIN[7] | GPIOE[31] | SD_D3(7) | MS_D3(4) | SDO(0) | -
#define HwPORTCFG9_UTXD0(X) ((X)*Hw12) // UTXD(0) = UTXD(0) | GPIOE[0] | - | - | - | -
#define HwPORTCFG9_URXD0(X) ((X)*Hw8) // URXD(0) = URXD(0) | GPIOE[1] | - | - | - | -
#define HwPORTCFG9_UCTS0(X) ((X)*Hw4) // UCTS(0) = UCTS(0) | GPIOE[2] | UTXD(4) | - | - | -
#define HwPORTCFG9_URTS0(X) ((X)*Hw0) // URTS(0) = URTS(0) | GPIOE[3] | URXD(4) | - | - | -
#define HwPORTCFG10 *(volatile unsigned long *)0xF005A028 // R/W, Port Configuration Register 10
#define HwPORTCFG10_UTXD1(X) ((X)*Hw28) // UTXD(1) = UTXD(1) | GPIOE[4] | - | - | - | -
#define HwPORTCFG10_URXD1(X) ((X)*Hw24) // URXD(1) = URXD(1) | GPIOE[5] | - | - | - | -
#define HwPORTCFG10_UCTS1(X) ((X)*Hw20) // UCTS(1) = UCTS(1) | GPIOE[6] | UTXD(5) | SD_CLK(4) | MS_CLK(2) | -
#define HwPORTCFG10_URTS1(X) ((X)*Hw16) // URTS(1) = URTS(1) | GPIOE[7] | URXD(5) | SD_CMD(4) | MS_BUS(2) | -
#define HwPORTCFG10_UTXD2(X) ((X)*Hw12) // UTXD(2) = UTXD(2) | GPIOE[8] | SFRM(4) | SD_D0(4) | MS_D0(2) | -
#define HwPORTCFG10_URXD2(X) ((X)*Hw8) // URXD(2) = URXD(2) | GPIOE[9] | SCLK(4) | SD_D1(4) | MS_D1(2) | -
#define HwPORTCFG10_UTXD3(X) ((X)*Hw4) // UTXD(3) = UTXD(3) | GPIOE[10] | SDI(4) | SD_D2(4) | MS_D2(2) | -
#define HwPORTCFG10_URXD3(X) ((X)*Hw0) // URXD(3) = URXD(3) | GPIOE[11] | SDO(4) | SD_D3(4) | MS_D3(2) | -
#define HwPORTCFG11 *(volatile unsigned long *)0xF005A02C // R/W, Port Configuration Register 11
#define HwPORTCFG11_BM(X) ((X)*Hw28) // BM[2:0] = BM[2:0] | GPIOF[31:29] | - | - | - | -
#define HwPORTCFG11_BCLK(X) ((X)*Hw24) // BCLK = BCLK | GPIOD[0] | - | - | - | -
#define HwPORTCFG11_LRCK(X) ((X)*Hw20) // LRCK = LRCK | GPIOD[1] | - | - | - | -
#define HwPORTCFG11_MCLK(X) ((X)*Hw16) // MCLK = MCLK | GPIOD[2] | - | - | - | -
#define HwPORTCFG11_DAO(X) ((X)*Hw12) // DAO = DAO | GPIOD[3] | - | - | - | -
#define HwPORTCFG11_DAI(X) ((X)*Hw8) // DAI = DAI | GPIOD[4] | - | - | - | -
#define HwPORTCFG11_GPIOA0(X) ((X)*Hw4) /*
GPIOA[0] = GPIOA[0] | SCL0 | - | - | - | -
GPIOA[1] = GPIOA[1] | SDA0 | - | - | - | -
*/
#define HwPORTCFG11_CCKI(X) ((X)*Hw0) // CCKI = CCKI | GPIOE[20] | - | - | - | -
#define HwPORTCFG12 *(volatile unsigned long *)0xF005A030 // R/W, Port Configuration Register 12
#define HwPORTCFG12_CCKO(X) ((X)*Hw28) // CCKO = CCKO | GPIOE[23] | - | - | - | -
#define HwPORTCFG12_CVS(X) ((X)*Hw24) // CVS = CVS | GPIOE[21] | - | - | - | -
#define HwPORTCFG12_CHS(X) ((X)*Hw20) // CHS = CHS | GPIOE[22] | - | - | - | -
#define HwPORTCFG12_CPD0(X) ((X)*Hw16) // CPD[0] = CPD[0] | GPIOE[12] | - | - | - | -
#define HwPORTCFG12_CPD1(X) ((X)*Hw12) // CPD[1] = CPD[1] | GPIOE[13] | - | - | - | -
#define HwPORTCFG12_CPD2(X) ((X)*Hw8) // CPD[2] = CPD[2] | GPIOE[14] | - | - | - | -
#define HwPORTCFG12_CPD3(X) ((X)*Hw4) // CPD[3] = CPD[3] | GPIOE[15] | - | - | - | -
#define HwPORTCFG12_CPD4(X) ((X)*Hw0) // CPD[4] = CPD[4] | GPIOE[16] | - | - | - | -
#define HwPORTCFG13 *(volatile unsigned long *)0xF005A034 // R/W, Port Configuration Register 13
#define HwPORTCFG13_CPD5(X) ((X)*Hw28) // CPD[5] = CPD[5] | GPIOE[17] | - | - | - | -
#define HwPORTCFG13_CPD6(X) ((X)*Hw24) // CPD[6] = CPD[6] | GPIOE[18] | - | - | - | -
#define HwPORTCFG13_CPD7(X) ((X)*Hw20) // CPD[7] = CPD[7] | GPIOE[19] | - | - | - | -
#define HwPORTCFG13_HPCSN(X) ((X)*Hw0) // HPCSN = HPCSN | GPIOF[20] | MS_D1(1) | SD_D1(1) | HDDXA[0] | LPDIN[20]
/************************************************************************
* LCD System INTERFACE Definition
************************************************************************/
//LCDSI Register map(0xF0000000)
//#define HwLCDSI 0xF0000000
typedef struct _LCDSI0{
volatile unsigned int CTRL0; // 0x400 R/W 0x00000000 Control register for LCDSI
}LCDSI0, *PLCDSI0;
typedef struct _LCDSI1{
volatile unsigned int CTRL1; // 0x800 R/W 0xA0229011 Control register for nCS0 when RS=0(for core access)
volatile unsigned int CTRL2; // 0x804 R/W 0xA0429021 Control register for nCS0 when RS=1(for core access)
volatile unsigned int CTRL3; // 0x808 R/W 0xA0129009 Control register for nCS1 when RS=0(for core access)
volatile unsigned int CTRL4; // 0x80C R/W 0xA0229011 Control register for nCS1 when RS=1(for core access)
volatile unsigned int CS0RS0; // 0x810 R/W -if this register is read or written, reading or writing operations are generated on nCS0 while RS = 0.
volatile unsigned int NOTDEFINE0; // 0x814
volatile unsigned int CS0RS1; // 0x818 R/W -if this register is read or written, reading or writing operations are generated on nCS0 while RS = 1.
volatile unsigned int NOTDEFINE1; // 0x81C
volatile unsigned int CS1RS0; // 0x820 R/W -if this register is read or written, reading or writing operations are generated on nCS1 while RS = 0.
volatile unsigned int NOTDEFINE2; // 0x824
volatile unsigned int CS1RS1; // 0x828 R/W -if this register is read or written, reading or writing operations are generated on nCS1 while RS = 1.
volatile unsigned int NOTDEFINE3; // 0x82C
volatile unsigned int CTRL5; // 0x830 R/W 0xA0229011 Control register for nCS0 when RS=0(for lcd access)
volatile unsigned int CTRL6; // 0x834 R/W 0xA0429021 Control register for nCS0 when RS=1(for lcd access)
volatile unsigned int CTRL7; // 0x838 R/W 0xA0129009 Control register for nCS1 when RS=0(for lcd access)
volatile unsigned int CTRL8; // 0x83C R/W 0xA0229011 Control register for nCS1 when RS=1(for lcd access)
}LCDSI1, *PLCDSI1;
/************************************************************************
* NTSC/PAL ENCODER COMPOSITE OUTPUT Definition
************************************************************************/
//STATA 0xF9000000
//#define HwNTSCPAL 0x90000000
typedef struct _NTSCPAL{
volatile unsigned int STATA; //0x00
volatile unsigned int ECMDA; //0x04
volatile unsigned int ECMDB; //0x08
volatile unsigned int GLK; //0x0C
volatile unsigned int SCH; //0x10
volatile unsigned int HUE; //0x14
volatile unsigned int SAT; //0x18
volatile unsigned int CONT; //0x1C
volatile unsigned int BRIGHT; //0x20
volatile unsigned int FSC_ADJM; //0x24
volatile unsigned int FSC_ADJL; //0x28
volatile unsigned int ECMDC; //0x2C
volatile unsigned int CSDLY; //0x30
volatile unsigned int NOTDEFINE0[3]; //0x34, 38, 3C
volatile unsigned int DACSEL; //0x40
volatile unsigned int DACSEL32; //0x44
volatile unsigned int DACSEL54; //0x48
volatile unsigned int DACLP; //0x4C
volatile unsigned int DACPD; //0x50
volatile unsigned int NOTDEFINE2[11]; //0x54, 58, 5C, 60, 64, 68, 6C, 70, 74, 78, 7C
volatile unsigned int ICNTL; //0x80
volatile unsigned int HVOFFST; //0x84
volatile unsigned int HOFFST; //0x88
volatile unsigned int VOFFST; //0x8C
volatile unsigned int HSVSO; //0x90
volatile unsigned int HSOB; //0x94
volatile unsigned int HSOE; //0x98
volatile unsigned int VSOB; //0x9C
volatile unsigned int VSOE; //0xA0
}NTSCPAL, *PNTSCPAL;
typedef struct _NTSCPALOP{
volatile unsigned int VENCON; //0xF90000800
volatile unsigned int VENCIF; //0xF90000804
}NTSCPALOP, *PNTSCPALOP;
/************************************************************************
* SCALER Definition
************************************************************************/
//Scaler Registers (Base Address = 0xF0070000)
//#define HwSCALER 0xF0070000
typedef struct _SCALER{
volatile unsigned int SRC_Y_BASE; // 0x000 R/W 0x00000000 Scaler source image Y base address register
volatile unsigned int SRC_U_BASE; // 0x004 R/W 0x00000000 Scaler source image U base address register
volatile unsigned int SRC_V_BASE; // 0x008 R/W 0x00000000 Scaler source image V base address register
volatile unsigned int SRC_SIZE; // 0x00c R/W 0x00000000 Source image size register
volatile unsigned int SRC_OFFSET; // 0x010 R/W 0x00000000 Source image line offset register
volatile unsigned int SRC_CONFIG; // 0x014 R/W 0x00000000 Source image configuration register
volatile unsigned int NOTDEFINE0[2]; // 0x018, 1C
volatile unsigned int DST_Y_BASE; // 0x020 R/W 0x00000000 Scaler destination image Y base address register
volatile unsigned int DST_U_BASE; // 0x024 R/W 0x00000000 Scaler destination image U base address register
volatile unsigned int DST_V_BASE; // 0x028 R/W 0x00000000 Scaler destination image V base address register
volatile unsigned int DST_SIZE; // 0x02c R/W 0x00000000 Destination image size register
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