tcc79x_structures.h

自己在wince的环境下做的一移动数字电视驱动

/************************************************************************
*	TCC79x WinCE Board Support Package
*	------------------------------------------------
*
*	FUNCTION	: TCC79x Structures DEFINE
*	MODEL		: TCC79x WinCE
*	CPU	NAME	: TCC79x
*	SOURCE		: TCC79xStructures.H
*
*	START DATE	: 2007 Aug. 21
*	MODIFY DATE	:
*	DEVISION	: DEPT. 4GROUP SYSTME 3 TEAM
*				: TELECHIPS, INC.
************************************************************************/

/************************************************************************
*	TCC79x Internal Register Definition File
************************************************************************/
#ifndef	__TCC79xSTRUCTURES_H__
#define	__TCC79xSTRUCTURES_H__


/************************************************************************
*	Bit Field Definition
************************************************************************/
#define	Hw37									(1LL << 37)
#define	Hw36									(1LL << 36)
#define	Hw35									(1LL << 35)
#define	Hw34									(1LL << 34)
#define	Hw33									(1LL << 33)
#define	Hw32									(1LL << 32)
#define	Hw31									0x80000000
#define	Hw30									0x40000000
#define	Hw29									0x20000000
#define	Hw28									0x10000000
#define	Hw27									0x08000000
#define	Hw26									0x04000000
#define	Hw25									0x02000000
#define	Hw24									0x01000000
#define	Hw23									0x00800000
#define	Hw22									0x00400000
#define	Hw21									0x00200000
#define	Hw20									0x00100000
#define	Hw19									0x00080000
#define	Hw18									0x00040000
#define	Hw17									0x00020000
#define	Hw16									0x00010000
#define	Hw15									0x00008000
#define	Hw14									0x00004000
#define	Hw13									0x00002000
#define	Hw12									0x00001000
#define	Hw11									0x00000800
#define	Hw10									0x00000400
#define	Hw9										0x00000200
#define	Hw8										0x00000100
#define	Hw7										0x00000080
#define	Hw6										0x00000040
#define	Hw5										0x00000020
#define	Hw4										0x00000010
#define	Hw3										0x00000008
#define	Hw2										0x00000004
#define	Hw1										0x00000002
#define	Hw0										0x00000001
#define	HwZERO									0x00000000


//#define	HwVERSION								*(volatile unsigned long *)0xE0001FFC
/************************************************************************
*	LCD INTERFACE Definition
************************************************************************/
//LCDC Register Map (Base Address = 0xF0000000)
//#define HwLCDC			0xF0000000
typedef struct _LCD{
	volatile unsigned int		LCTRL;				// 0x00 W 0x00000000 LCD Control Register
	volatile unsigned int		LBC;				// 0x04 W 0x00000000 LCD Background Color Register
	volatile unsigned int		LCLKDIV;			// 0x08 W 0x00000000 LCD Clock Divider Register
	volatile unsigned int		LHTIME1;			// 0x0C W 0x00000000 LCD Horizontal Timing Register 1
	volatile unsigned int		LHTIME2;			// 0x10 W 0x00000000 LCD Horizontal Timing Register 2
	volatile unsigned int		LVTIME1;			// 0x14 W 0x00000000 LCD Vertical Timing Register 1
	volatile unsigned int		LVTIME2;			// 0x18 W 0x00000000 LCD Vertical Timing Register 2
	volatile unsigned int		LVTIME3;			// 0x1C W 0x00000000 LCD Vertical Timing Register 3
	volatile unsigned int		LVTIME4;			// 0x20 W 0x00000000 LCD Vertical Timing Register 4
	volatile unsigned int		LLUTR;				// 0x24 W 0x00000000 LCD Lookup Register for Red
	volatile unsigned int		LLUTG;				// 0x28 W 0x00000000 LCD Lookup Register for Green
	volatile unsigned int		LLUTB;				// 0x2C W 0x00000000 LCD Lookup Register for Blue
	volatile unsigned int		LDP7L;				// 0x30 W 0x4d2b3401 LCD Modulo 7 Dithering Pattern (low)
	volatile unsigned int		LDP7H;				// 0x34 W 0x0000003f LCD Modulo 7 Dithering Pattern (high)
	volatile unsigned int		LDP5;				// 0x38 W 0x1d0b0610 LCD Modulo 5 Dithering Pattern Register
	volatile unsigned int		LDP4;				// 0x3C W 0x00000768 LCD Modulo 4 Dithering Pattern Register
	volatile unsigned int		LDP3;				// 0x40 W 0x00000034 LCD 3-bit Dithering Pattern Register
	volatile unsigned int		LCP1;				// 0x44 W 0x000000ff LCD Clipping Register1
	volatile unsigned int		LCP2;				// 0x48 W 0x000000ff LCD Clipping Register2
	volatile unsigned int		LK1;				// 0x4C W 0x00000000 LCD Keying Register 1
	volatile unsigned int		LK2;				// 0x50 W 0x00000000 LCD Keying Register 2
	volatile unsigned int		LKM1;				// 0x54 W 0x00000000 LCD Keying Mask Register 1
	volatile unsigned int		LKM2;				// 0x58 W 0x00000000 LCD Keying Mask Register 2
	volatile unsigned int		LDS;				// 0x5C W 0x00000000 LCD Display Size Register
	volatile unsigned int		LSTATUS;			// 0x60 R/CLR 0x00000000 LCD Status Register
	volatile unsigned int		LIM;				// 0x64 W 0x0000001f LCD Interrupt Register.
	volatile unsigned int		LI0C;				// 0x68 W 0x00000000 LCD Image 0 Control Register
	volatile unsigned int		LI0P;				// 0x6C W 0x00000000 LCD Image 0 Position Register
	volatile unsigned int		LI0S;				// 0x70 W 0x00000000 LCD Image 0 Size Register
	volatile unsigned int		LI0BA0;				// 0x74 W 0x00000000 LCD Image 0 Base Address 0 Register.
	volatile unsigned int		LI0CA;				// 0x78 W 0x00000000 LCD Image 0 Current Address Register.
	volatile unsigned int		LI0BA1;				// 0x7C W 0x00000000 LCD Image 0 Base Address 1 Register
	volatile unsigned int		LI0BA2;				// 0x80 W 0x00000000 LCD Image 0 Base Address 2 Register
	volatile unsigned int		LI0O;				// 0x84 W 0x00000000 LCD Image 0 Offset Register
	volatile unsigned int		LI0SR;				// 0x88 W 0x00000000 LCD Image 0 Scale ratio
	volatile unsigned int		LI1C;				// 0x8C W 0x00000000 LCD Image 1 Control Register
	volatile unsigned int		LI1P;				// 0x90 W 0x00000000 LCD Image 1 Position Register
	volatile unsigned int		LI1S;				// 0x94 W 0x00000000 LCD Image 1 Size Register
	volatile unsigned int		LI1BA0;				// 0x98 W 0x00000000 LCD Image 1 Base Address 0 Register.
	volatile unsigned int		LI1CA;				// 0x9C W 0x00000000 LCD Image 1 Current Address Register.
	volatile unsigned int		NOTDEFINE0;			// 0xA0 0x00000000
	volatile unsigned int		NOTDEFINE1;			// 0xA4 0x00000000
	volatile unsigned int		LI1O;				// 0xA8 W 0x00000000 LCD Image 1 Offset Register
	volatile unsigned int		LI1SR;				// 0xAC W 0x00000000 LCD Image 1 Scale ratio-
	volatile unsigned int		LI2C;				// 0xB0 W 0x00000000 LCD Image 2 Control Register
	volatile unsigned int		LI2P;				// 0xB4 W 0x00000000 LCD Image 2 Position Register
	volatile unsigned int		LI2S;				// 0xB8 W 0x00000000 LCD Image 2 Size Register
	volatile unsigned int		LI2BA0;				// 0xBC W 0x00000000 LCD Image 2 Base Address 0 Register.
	volatile unsigned int		LI2CA;				// 0xC0 W 0x00000000 LCD Image 2 Current Address Register.
	volatile unsigned int		NOTDEFINE2;			// 0xC4 0x00000000
	volatile unsigned int		NOTDEFINE3;			// 0xC8 0x00000000
	volatile unsigned int		LI2O;				// 0xCC W 0x00000000 LCD Image 2 Offset Register
	volatile unsigned int		LI2SR;				// 0xD0 W 0x00000000 LCD Image 2 Scale ratio
	volatile unsigned int		DLCTRL;				// 0xD4 W 0x00000000 Dual LCD Control Register
	volatile unsigned int		NOTDEFINE4;			// 0xD8 0x00000000
	volatile unsigned int		DLCSA0;				// 0xDC W 0x00000000 Dual LCD Configuration Start Address 0
	volatile unsigned int		DLCSA1;				// 0xE0 W 0x00000000 Dual LCD Configuration Start Address 1
	//volatile unsigned int		LCDLUT;				// 0xC00 W - LCD Lookup Table.
}LCD, *PLCD;

#define	HwPORTCFG0								*(volatile unsigned long *)0xF005A000	// R/W, Port Configuration Register 0
	#define	HwPORTCFG0_LPD23(X)	((X)*Hw28)	// LPD[23]		= LPD[23]		| -			| GPIOC[23]	| SD_CMD(0)	| MS_BUS(0)	| SFRM(10)
	#define	HwPORTCFG0_LPD22(X)	((X)*Hw24)	// LPD[22]		= LPD[22]		| -			| GPIOC[22]	| SD_CLK(0)	| MS_CLK(0)	| SCLK(10)
	#define	HwPORTCFG0_LPD21(X)	((X)*Hw20)	// LPD[21]		= LPD[21]		| -			| GPIOC[21]	| SD_D0(0)	| MS_D0(0)	| SDI(10)
	#define	HwPORTCFG0_LPD20(X)	((X)*Hw16)	// LPD[20]		= LPD[20]		| -			| GPIOC[20]	| SD_D1(0)	| MS_D1(0)	| SDO(10)
	#define	HwPORTCFG0_LPD19(X)	((X)*Hw12)	// LPD[19:18]		= LPD[19:18]	| -			| GPIOC[19:18]	| SD_D[2:3](0)	| MS_D[2:3](0)	| -
	#define	HwPORTCFG0_LCD18(X)	((X)*Hw8)	// LPD[17:16]		= LPD[17:16]	| LXD[17:16]	| GPIOC[17:16]	| -			| -			| -
	#define	HwPORTCFG0_LCD16(X)	((X)*Hw4)	// LPD[15:8]		= LPD[15:8]	| LXD[15:8]	| GPIOC[15:8]	| -			| -			| -
	#define	HwPORTCFG0_LCD8(X)		((X)*Hw0)	// LPD[7:0]		= LPD[7:0]	| LXD[7:0]	| GPIOC[7:0]	| -			| -			| -

#define	HwPORTCFG1								*(volatile unsigned long *)0xF005A004	// R/W, Port Configuration Register 1
	#define	HwPORTCFG1_LDE(X)		((X)*Hw28)	// LBIAS			= LDE		| LWEN		| GPIOC[25]	| -			| -			| -
	#define	HwPORTCFG1_LCK(X)		((X)*Hw24)	// LCK			= LCK		| LOEN		| GPIOC[26]	| -			| -			| -
	#define	HwPORTCFG1_LHS(X)		((X)*Hw20)	// LHS			= LHS		| LXA		| GPIOC[27]	| -			| -			| -
	#define	HwPORTCFG1_LVS(X)		((X)*Hw16)	// LVS			= LVS		| LCSN[0]		| GPIOC[28]	| -			| -			| -
	#define	HwPORTCFG1_LCS(X)		((X)*Hw12)	// GPIOC[29]		= GPIOC[29]	| LCSN[1]		| GPIOC[29]	| -			| -			| -
	#define	HwPORTCFG1_GPIOC30(X)	((X)*Hw8)	// GPIOC[30]		= GPIOC[30]	| GPIOC[30]	| GPIOC[30]	| -			| -			| -
	#define	HwPORTCFG1_GPIOC31(X)	((X)*Hw4)	// GPIOC[31]		= GPIOC[31]	| GPIOC[31]	| GPIOC[31]	| -			| -			| -
	#define	HwPORTCFG1_GPIOF27(X)	((X)*Hw0)	// GPIOF[27]		= -			| GPIOF[27]	| SFRM(9)		| NANDRDY3	| -			| LDE_IN

#define	HwPORTCFG2								*(volatile unsigned long *)0xF005A008	// R/W, Port Configuration Register 2
	#define	HwPORTCFG2_GPIOF26(X)	((X)*Hw28)	// GPIOF[26]		= -			| GPIOF[26]	| SCLK(9)		| NDRDY2		| HDDRDY		| LCLK_IN
	#define	HwPORTCFG2_GPIOF25(X)	((X)*Hw24)	// GPIOF[25]		= -			| GPIOF[25]	| SDI(9)		| NDCSN3		| -			| LVS_IN
	#define	HwPORTCFG2_HPCSN_L(X)	((X)*Hw20)	// HPCSN_L		= HPCSN_L	| GPIOF[24]	| SDO(9)		| NDCSN2		| HDDAK		| LHS_IN
	#define	HwPORTCFG2_HPCTRL(X)	((X)*Hw16)	/*
													HPINTO		= HPINTO	| GPIOF[23]	| MS_CLK(1)	| SD_CLK(1)	| HDDRQ		| LPDIN[23]
													HPXA[1]		= HPXA[1]	| GPIOF[22]	| MS_BUS(1)	| SD_CMD(1)	| HDDXA[2]	| LPDIN[22]
													HPXA[0]		= HPXA[0]	| GPIOF[21]	| MS_D0(1)	| SD_D0(1)	| HDDXA[1]	| LPDIN[21]
													HPWRN		= HPWRN		| GPIOF[19]	| MS_D2(1)	| SD_D2(1)	| HDDIOW	| LPDIN[19]
													HPRDN		= HPRDN		| GPIOF[18]	| MS_D3(1)	| SD_D3(1)	| HDDIOR	| LPDIN[18]
												*/
	#define	HwPORTCFG2_HPXD17(X)	((X)*Hw12)	/*
													HPXD[17]	= HPXD[17]	| GPIOF[17]	| SD_CLK(3)	| SD_CLK(2)	| HDDCSN1	| LPDIN[17]
													HPXD[16]	= HPXD[16]	| GPIOF[16]	| SD_CMD(3)	| SD_CMD(2)	| HDDCSN0	| LPDIN[16]
												*/
	#define	HwPORTCFG2_HPXD15(X)	((X)*Hw8)	// HPXD[15:12]	= HPXD[15:12]	| GPIOF[15:12]	| NDXD[15:12]	| SD_D[7:4](2)	| HDDXD[15:12]| LPDIN[15:12]
	#define	HwPORTCFG2_HPXD11(X)	((X)*Hw4)	// HPXD[11:8]		= HPXD[11:8]	| GPIOF[11:8]	| NDXD[11:8]	| SD_D[3:0](2)	| HDDXD[11:8]	| LPDIN[11:8]
	#define	HwPORTCFG2_HPXD7(X)	((X)*Hw0)	// HPXD[7]		= HPXD[7]	| GPIOF[7]	| SD_D7(3)	| SFRM(8)		| HDDXD[7]	| LPDIN[7]

#define	HwPORTCFG3								*(volatile unsigned long *)0xF005A00C	// R/W, Port Configuration Register 3
	#define	HwPORTCFG3_HPXD6(X)	((X)*Hw28)	// HPXD[6]		= HPXD[6]	| GPIOF[6]	| SD_D6(3)	| SCLK(8)		| HDDXD[6]	| LPDIN[6]
	#define	HwPORTCFG3_HPXD5(X)	((X)*Hw24)	// HPXD[5]		= HPXD[5]	| GPIOF[5]	| SD_D5(3)	| SDI(8)		| HDDXD[5]	| LPDIN[5]
	#define	HwPORTCFG3_HPXD4(X)	((X)*Hw20)	// HPXD[4]		= HPXD[4]	| GPIOF[4]	| SD_D4(3)	| SDO(8)		| HDDXD[4]	| LPDIN[4]
	#define	HwPORTCFG3_HPXD3(X)	((X)*Hw16)	// HPXD[3]		= HPXD[3]	| GPIOF[3]	| SD_D3(3)	| SFRM(7)		| HDDXD[3]	| LPDIN[3]
	#define	HwPORTCFG3_HPXD2(X)	((X)*Hw12)	// HPXD[2]		= HPXD[2]	| GPIOF[2]	| SD_D2(3)	| SCLK(7)		| HDDXD[2]	| LPDIN[2]
	#define	HwPORTCFG3_HPXD1(X)	((X)*Hw8)	// HPXD[1]		= HPXD[1]	| GPIOF[1]	| SD_D1(3)	| SDI(7)		| HDDXD[1]	| LPDIN[1]
	#define	HwPORTCFG3_HPXD0(X)	((X)*Hw4)	// HPXD[0]		= HPXD[0]	| GPIOF[0]	| SD_D0(3)	| SDO(7)		| HDDXD[0]	| LPDIN[0]
	#define	HwPORTCFG3_SCMD0(X)	((X)*Hw0)	// SCMD0			= SFRM(6)	| GPIOD[5]	| -			| -			| -			| -

#define	HwPORTCFG4								*(volatile unsigned long *)0xF005A010	// R/W, Port Configuration Register 4
	#define	HwPORTCFG4_SCLK0(X)	((X)*Hw28)	// SCLK0			= SCLK(6)		| GPIOD[6]	| -			| -			| -			| -
	#define	HwPORTCFG4_SDI0(X)		((X)*Hw24)	// SDI0			= SDI(6)		| GPIOD[7]	| -			| -			| -			| -
	#define	HwPORTCFG4_SDO0(X)		((X)*Hw20)	// SDO0			= SDO(6)		| GPIOD[8]	| -			| -			| -			| -