📄 tcc78xphysical.h
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#define HwUDMACTRL_ITL1 HwZERO // Single Transfer
#define HwUDMACTRL_ITL4 Hw23 // 4 (32bit data) (vcnt >= 4)
#define HwUDMACTRL_ITL8 Hw24 // 8 (32bit data) (vcnt >= 8)
#define HwUDMACTRL_ITL12 (Hw24+Hw23) // 12 (32bit data) (vcnt >= 12)
#define HwUDMACTRL_AHB1 HwZERO // The hold margin of the data to be transferred has one AHB clock period
#define HwUDMACTRL_AHB2 Hw15 // The hold margin of the data to be transferred has two AHB clock period
#define HwUDMACTRL_HTB_OFF HwZERO //
#define HwUDMACTRL_HTB_ON Hw5 // HOST terminate operation when CTCNT reaches zero.
#define HwUDMACTRL_TS16 HwZERO // 16bit Transfer Mode (in Internal Bus)
#define HwUDMACTRL_TS32 Hw4 // 32bit Transfer Mode (in Internal Bus)
#define HwUDMACTRL_BS_OFF HwZERO //
#define HwUDMACTRL_BS_ON Hw3 // BUS Share Mode
#define HwUDMACTRL_HT_OFF HwZERO //
#define HwUDMACTRL_HT_ON Hw2 // HOST Termination
#define HwUDMACTRL_UIO_IN HwZERO // UDMA-IN Mode
#define HwUDMACTRL_UIO_OUT Hw1 // UDMA-OUT Mode
#define HwUDMACTRL_UEN_OFF HwZERO //
#define HwUDMACTRL_UEN_ON Hw0 // UDMA Enable Bit
#define HwIDMACTRL *(volatile unsigned long *)0xF0030048 // R/W, IDMA control register
#define HwIDMACTRL_ARB_OFF HwZERO //
#define HwIDMACTRL_ARB_ON Hw4 // IDMA transfer executed with arbitration transfer
#define HwIDMACTRL_LOC_OFF HwZERO //
#define HwIDMACTRL_LOC_ON Hw3 // DMA transfer executed with lock transfer
#define HwIDMACTRL_CON HwZERO // DMA transfer begins from CSAR/CDAR address
#define HwIDMACTRL_CON_MEAN Hw2 // DMA transfer begins from CSAR/CDAR address, It must be used after the former transfer has been executed, so that CSAR and CDAR contaion a meaningful value
#define HwIDMACTRL_REP_AUTODIS HwZERO // When UDMA operation end, IDE bit is automatically disabled
#define HwIDMACTRL_REP_NOTDIS Hw1 // When UDMA operation end, IDE bit is not disabled
#define HwIDMACTRL_IDE_OFF HwZERO //
#define HwIDMACTRL_IDE_ON Hw0 // Internal DMA(IDMA) enable bit
#define HwIDMASA *(volatile unsigned long *)0xF003004C // R/W, IDMA source address register
#define HwIDMASP *(volatile unsigned long *)0xF0030050 // R/W, IDMA source parameter register
#define HwIDMACSA *(volatile unsigned long *)0xF0030054 // R, IDMA current source address register
#define HwIDMADA *(volatile unsigned long *)0xF0030058 // R/W, destination address IDMA register
#define HwIDMADP *(volatile unsigned long *)0xF003005C // R/W, destination parameter IDMA register
#define HwIDMACDA *(volatile unsigned long *)0xF0030060 // R, current destination address IDMA register
#define HwIDEINT *(volatile unsigned long *)0xF0030064 // R/W, IDE interrupt register
#define HwIDEINT_UB Hw31 // UDMA is Busy(1), State of UDMA is IDLE(0)
#define HwIDEINT_NWA_ON HwZERO // Word(32bit) aligned
#define HwIDEINT_NWA_OFF Hw30 // Not Word(32bit) aligned
#define HwIDEINT_DT_OFF HwZERO // Device did not terminate operation
#define HwIDEINT_DT_ON Hw29 // Device terminated operation
#define HwIDEINT_URS_AUTOCLR HwZERO // UDMA request from the device is not active or automatically clear
#define HwIDEINT_URS_ACTIVE Hw11 // UDMA request from the device is active
#define HwIDEINT_FES_GOOD HwZERO // Not FIFO Error
#define HwIDEINT_FES_ERROR Hw10 // FIFO Error
#define HwIDEINT_TRS_AUTOCLR HwZERO // Trigger level request is not active or automatically clear
#define HwIDEINT_TRS_ACTIVE Hw9 // Trigger level request is active
#define HwIDEINT_OPE_OFF HwZERO // Host or Device dose not terminate operation yet
#define HwIDEINT_OPE_ON Hw8 // Host or Device terminate operation
#define HwIDEINT_URE_DIS HwZERO // UDMA request interrupt is disabled
#define HwIDEINT_URE_EN Hw3 // UDMA request interrupt is enabled
#define HwIDEINT_FEE_DIS HwZERO // FIFO Error interrupt is disabled
#define HwIDEINT_FEE_EN Hw2 // FIFO Error interrupt is enabled
#define HwIDEINT_TRE_DIS HwZERO // Trigger level interrupt is disabled
#define HwIDEINT_TRE_EN Hw1 // Trigger level interrupt is enabled
#define HwUDMATCNT *(volatile unsigned long *)0xF0030068 // R/W, UDMA transfer counter register
#define HwUDMAIN *(volatile unsigned long *)0xF003006C // R, UDMA-IN access register
#define HwUDMAOUT *(volatile unsigned long *)0xF0030070 // W, UDMA-OUT access register
#define HwUDMACRC *(volatile unsigned long *)0xF0030074 // R, UDMA CRC register
#define HwUDMACTCNT *(volatile unsigned long *)0xF0030078 // R, UDMA status register
/***********************************************************************
* DMA Controller Register Define (Base Addr = 0xF0040000)
************************************************************************/
#define HwST_SADR0 *(volatile unsigned long *)0xF0040000 // R/W, Start Address of Source Block Register
#define HwSPARAM0 *(volatile unsigned long *)0xF0040004 // R/W, Parameter of Source Block Register
#define HwC_SADR0 *(volatile unsigned long *)0xF004000C // R, Current Address of Source Block Register
#define HwST_DADR0 *(volatile unsigned long *)0xF0040010 // R/W, Start Address of Destination Block Register
#define HwDPARAM0 *(volatile unsigned long *)0xF0040014 // R/W, Parameter of Destination Block Register
#define HwC_DADR0 *(volatile unsigned long *)0xF004001C // R, Current Address of Destination Block Register
#define HwHCOUNT0 *(volatile unsigned long *)0xF0040020 // R/W, Initial and Current Hop Count Register
#define HwCHCTRL0 *(volatile unsigned long *)0xF0040024 // R/W, Channel Control Register
#define HwCHCTRL0_DMASEL_UART1_RX Hw30 // Connected Hardware = UART Channel 1 Receiver
#define HwCHCTRL0_DMASEL_UART1_TX Hw29 // Connected Hardware = UART Channel 1 Transmitter
#define HwCHCTRL0_DMASEL_UART0_RX Hw28 // Connected Hardware = UART Channel 0 Receiver
#define HwCHCTRL0_DMASEL_UART0_TX Hw27 // Connected Hardware = UART Channel 0 Transmitter
#define HwCHCTRL0_DMASEL_GSIO Hw26 // Connected Hardware = GSIO Controller
#define HwCHCTRL0_DMASEL_I2C_CH1 Hw25 // Connected Hardware = I2C Controller Channel 1
#define HwCHCTRL0_DMASEL_DAIR Hw24 // Connected Hardware = DAI Receiver
#define HwCHCTRL0_DMASEL_DAIT Hw23 // Connected Hardware = DAI Transmitter
#define HwCHCTRL0_DMASEL_CDIF Hw22 // Connected Hardware = CD I/F
#define HwCHCTRL0_DMASEL_SPDIF_UDATA Hw21 // Connected Hardware = SPDIF User Data
#define HwCHCTRL0_DMASEL_SPDIF_PDATA Hw20 // Connected Hardware = SPDIF Packet(Audio) Data
#define HwCHCTRL0_DMASEL_I2C_CH0 Hw19 // Connected Hardware = I2C Controller Channel 0
#define HwCHCTRL0_DMASEL_NFC Hw18 // Connected Hardware = NAND Flash Controller
#define HwCHCTRL0_DMASEL_MSTICK Hw17 // Connected Hardware = Memory Stick
#define HwCHCTRL0_DMASEL_SDMMC Hw16 // Connected Hardware = SD/MMC
#define HwCHCTRL0_CONT_C Hw15 // DMA transfer begins from C_SADR / C_DADR address. It must be used after the former transfer has been executed, so that C_SADR and C_DADR contain a meaningful vlaue
#define HwCHCTRL0_SWAP_EN Hw14 // Swap Channel 1 Data
#define HwCHCTRL0_SYNC_EN Hw13 // Synchronize Hardware Request
#define HwCHCTRL0_HRD_W Hw12 // ACK/EOT signals are issued When DMA-Write Operation
#define HwCHCTRL0_LOCK_EN Hw11 // DMA transfer executed with lock transfer
#define HwCHCTRL0_BST_NOARB Hw10 // DMA transfer executed with no arbitration(burst operation)
#define HwCHCTRL0_TYPE_SE HwZERO // SINGLE transfer with edge-triggered detection
#define HwCHCTRL0_TYPE_SL (Hw9+Hw8) // SINGLE transfer with level-triggered detection
#define HwCHCTRL0_TYPE_HW Hw8 // HW transfer
#define HwCHCTRL0_TYPE_SW Hw9 // SW transfer
#define HwCHCTRL0_BSIZE_1 HwZERO // 1 Burst transfer consists of 1 read or write cycle
#define HwCHCTRL0_BSIZE_2 Hw6 // 1 Burst transfer consists of 2 read or write cycle
#define HwCHCTRL0_BSIZE_4 Hw7 // 1 Burst transfer consists of 4 read or write cycle
#define HwCHCTRL0_BSIZE_8 (Hw7+Hw6) // 1 Burst transfer consists of 8 read or write cycle
#define HwCHCTRL0_WSIZE_8 HwZERO // Each cycle read or write 8bit data
#define HwCHCTRL0_WSIZE_16 Hw4 // Each cycle read or write 16bit data
#define HwCHCTRL0_WSIZE_32 Hw5 // Each cycle read or write 32bit data
#define HwCHCTRL0_FLAG Hw3 // W : Clears FLAG to 0, R : Represents that all hop of transfer are fulfilled
#define HwCHCTRL0_IEN_EN Hw2 // At the same time the FLAG goes to 1, DMA interrupt request is generated
#define HwCHCTRL0_REP_EN Hw1 // The DMA channel remains enabled. When another DMA request has occurred, the DMA channel start transfer data again with the same manner(type,address,increment,mask) as the latest transfer of that channel
#define HwCHCTRL0_EN_EN Hw0 // DMA channel is enabled. If software type transfer is selected, this bit generates DMA request directly, or if hardware type transfer is used, the selected interrupt request flag generate DMA request
#define HwRPTCTRL0 *(volatile unsigned long *)0xF0040028 // R/W, Repeat Control Register
#define HwRPTCTRL0_DRI_LAST Hw31 // DAM interrupt occur is occurred at the last DMA Repeated DMA operation
#define HwRPTCTRL0_DEOT_LAST Hw30 // EOT signal is occurred at the last Repeated DAM operation in HW(including Single) transfer Mode
#define HwST_SADR1 *(volatile unsigned long *)0xF0040100 // R/W, Start Address of Source Block Register
#define HwSPARAM1 *(volatile unsigned long *)0xF0040104 // R/W, Parameter of Source Block Register
#define HwC_SADR1 *(volatile unsigned long *)0xF004010C // R, Current Address of Source Block Register
#define HwST_DADR1 *(volatile unsigned long *)0xF0040110 // R/W, Start Address of Destination Block Register
#define HwDPARAM1 *(volatile unsigned long *)0xF0040114 // R/W, Parameter of Destination Block Register
#define HwC_DADR1 *(volatile unsigned long *)0xF004011C // R, Current Address of Destination Block Register
#define HwHCOUNT1 *(volatile unsigned long *)0xF0040120 // R/W, Initial and Current Hop Count Register
#define HwCHCTRL1 *(volatile unsigned long *)0xF0040124 // R/W, Channel Control Register
#define HwCHCTRL1_DMASEL_UART1_RX Hw30 // Connected Hardware = UART Channel 1 Receiver
#define HwCHCTRL1_DMASEL_UART1_TX Hw29 // Connected Hardware = UART Channel 1 Transmitter
#define HwCHCTRL1_DMASEL_UART0_RX Hw28 // Connected Hardware = UART Channel 0 Receiver
#define HwCHCTRL1_DMASEL_UART0_TX Hw27 // Connected Hardware = UART Channel 0 Transmitter
#define HwCHCTRL1_DMASEL_GSIO Hw26 // Connected Hardware = GSIO Controller
#define HwCHCTRL1_DMASEL_I2C_CH1 Hw25 // Connected Hardware = I2C Controller Channel 1
#define HwCHCTRL1_DMASEL_DAIR Hw24 // Connected Hardware = DAI Receiver
#define HwCHCTRL1_DMASEL_DAIT Hw23 // Connected Hardware = DAI Transmitter
#define HwCHCTRL1_DMASEL_CDIF Hw22 // Connected Hardware = CD I/F
#define HwCHCTRL1_DMASEL_SPDIF_UDATA Hw21 // Connected Hardware = SPDIF User Data
#define HwCHCTRL1_DMASEL_SPDIF_PDATA Hw20 // Connected Hardware = SPDIF Packet(Audio) Data
#define HwCHCTRL1_DMASEL_I2C_CH0 Hw19 // Connected Hardware = I2C Controller Channel 0
#define HwCHCTRL1_DMASEL_NFC Hw18 // Connected Hardware = NAND Flash Controller
#define HwCHCTRL1_DMASEL_MSTICK Hw17 // Connected Hardware = Memory Stick
#define HwCHCTRL1_DMASEL_SDMMC Hw16 // Connected Hardware = SD/MMC
#define HwCHCTRL1_CONT_C Hw15 // DMA transfer begins from C_SADR / C_DADR address. It must be used after the former transfer has been executed, so that C_SADR and C_DADR contain a meaningful vlaue
#define HwCHCTRL1_SWAP_EN Hw14 // Swap Channel 1 Data
#define HwCHCTRL1_SYNC_EN Hw13 // Synchronize Hardware Request
#define HwCHCTRL1_HRD_W Hw12 // ACK/EOT signals are issued When DMA-Write Operation
#define HwCHCTRL1_LOCK_EN Hw11 // DMA transfer executed with lock transfer
#define HwCHCTRL1_BST_NOARB Hw10 // DMA transfer executed with no arbitration(burst operation)
#define HwCHCTRL1_TYPE_SE HwZERO // SINGLE transfer with edge-triggered detection
#define HwCHCTRL1_TYPE_SL (Hw9+Hw8) // SINGLE transfer with level-triggered detection
#define HwCHCTRL1_TYPE_HW Hw8 // HW transfer
#define HwCHCTRL1_TYPE_SW Hw9 // SW transfer
#define HwCHCTRL1_BSIZE_1 HwZERO // 1 Burst transfer consists of 1 read or write cycle
#define HwCHCTRL1_BSIZE_2 Hw6 // 1 Burst transfer consists of 2 read or write cycle
#define HwCHCTRL1_BSIZE_4 Hw7 // 1 Burst transfer consists of 4 read or write cycle
#define HwCHCTRL1_BSIZE_8 (Hw7+Hw6) // 1 Burst transfer consists of 8 read or write cycle
#define HwCHCTRL1_WSIZE_8 HwZERO // Each cycle read or write 8bit data
#define HwCHCTRL1_WSIZE_16 Hw4 // Each cycle read or write 16bit data
#define HwCHCTRL1_WSIZE_32 Hw5 // Each cycle read or write 32bit data
#define HwCHCTRL1_FLAG Hw3 // W : Clears FLAG to 0, R : Represents that all hop of transfer are fulfilled
#define HwCHCTRL1_IEN_EN Hw2 // At the same time the FLAG goes to 1, DMA interrupt request is generated
#define HwCHCTRL1_REP_EN Hw1 // The DMA channel remains enabled. When another DMA request has occurred, the DMA channel start transfer data again with the same manner(type,address,increment,mask) as the latest transfer of that channel
#define HwCHCTRL1_EN_EN Hw0 // DMA channel is enabled. If software type transfer is selected, this bit generates DMA request directly, or if hardware type transfer is used, the selected interrupt request flag generate DMA request
#define HwRPTCTRL1 *(volatile unsigned long *)0xF0⌨️ 快捷键说明
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