tcc78xphysical.h

自己在wince的环境下做的一移动数字电视驱动

                                        	
#define	HwESR									*(volatile unsigned long *)0xF001002C	// R/W, Endpoint Status Register
#define	HwESR_FUDR								Hw15									// FIFO Underflow
#define	HwESR_FOVF								Hw14									// FIFO Overflow
#define	HwESR_FPID_ON							Hw11									// First OUT packet cannot generate interrupt in OUT DMA operation.
#define	HwESR_FPID_OFF							~Hw11									// First OUT packet generate interrupt in OUT DMA operation.
#define	HwESR_OSD								Hw10									// OUT packet is first received after DMA registers are set.
#define	HwESR_DTCZ								Hw9										// DMA Total Count Zero
#define	HwESR_SPT								Hw8										// Short Packet Received during OUT DMA operation
#define	HwESR_DOM								Hw7										// Dual Operation Mode (Max packet = FIFO size / 2)
#define	HwESR_FFS								Hw6										// FIFO Flushed (Cleared by FLUSH of HwECR register)
#define	HwESR_FSC								Hw5										// Function Stall Condition is sent to Host.
#define	HwESR_LWO								Hw4										// Last Word Odd
#define	HwESR_PSIF_NP							HwZERO									// No Packet in FIFO
#define	HwESR_PSIF_1P							Hw2										// 1 Packet in FIFO
#define	HwESR_PSIF_2P							Hw3										// 2 Packets in FIFO
#define	HwESR_TPS								Hw1										// TX Packet Success
#define	HwESR_RPS								Hw0										// RX Packet Success
                                        	
#define	HwECR									*(volatile unsigned long *)0xF0010030	// R/W, Endpoint Control Register
#define	HwECR_INHLD_EN							Hw12									// In-Packet Hold Enable (USB sends NAK regardless of IN FIFO status)
#define	HwECR_INHLD_DIS							~Hw12									// In-Packet Hold Disable (USB sends IN data)
#define	HwECR_OUTHLD_EN							Hw11									// Out-Packet Hold Enable (USB doesn't accept OUT data)
#define	HwECR_OUTHLD_DIS						~Hw11									// Out-Packet Hold Disable (USB accept OUT data)
#define	HwECR_TNPMF_1T							Hw9										// 1 Transaction Per MicroFrame
#define	HwECR_TNPMF_2T							Hw10									// 2 Transactions Per MicroFrame
#define	HwECR_TNPMF_3T							(Hw10+Hw9)								// 3 Transactions Per MicroFrame
#define	HwECR_DUEN_EN							Hw7										// Dual FIFO Mode Enable
#define	HwECR_DUEN_DIS							~Hw7									// Dual FIFO Mode Disable
#define	HwECR_FLUSH_EN							Hw6										// FIFO is Flushed (automatically cleared after writing)
#define	HwECR_TTE_EN							Hw5										// TX Toggle Forcing Enable
#define	HwECR_TTE_DIS							~Hw5									// TX Toggle Forcing Disable
#define	HwECR_TTS_PID0							HwZERO									// TX Data Toggle bit = PID 0
#define	HwECR_TTS_PID1							Hw3										// TX Data Toggle bit = PID 1
#define	HwECR_TTS_PID2							Hw4										// TX Data Toggle bit = PID 2 (ISO only)
#define	HwECR_TTS_PIDM							(Hw4+Hw3)								// TX Data Toggle bit = PID M (ISO only)
#define	HwECR_CDP_CLR							Hw2										// Clear Data PID register
#define	HwECR_ESS_SET							Hw1										// send STALL handshake to Host
#define	HwECR_ESS_CLR							~Hw1									// stop sending STALL handshake
#define	HwECR_TZLS_SET							Hw0										// Transmit Zero Length Data (active when TTE is set)
#define	HwECR_TZLS_CLR							~Hw0									// Stop Transmitting Zero Length Data (active when TTE is set)
                                        	
#define	HwBRCR									*(volatile unsigned long *)0xF0010034	// R, Byte Read Counter (Half-word unit)
                                        	
#define	HwBWCR									*(volatile unsigned long *)0xF0010038	// W, Byte Write Counter (Byte unit)
                                        	
#define	HwMPR									*(volatile unsigned long *)0xF001003C	// R/W, Max Packet Register (Byte unit)
                                        	
#define	HwDCR									*(volatile unsigned long *)0xF0010040	// R/W, DMA Control Register
#define	HwDCR_ARDRD_ON							Hw5										// Auto RX DMA Run Disable On
#define	HwDCR_ARDRD_OFF							~Hw5									// Auto RX DMA Run Disable Off
#define	HwDCR_FMDE_EN							Hw4										// Fly Mode DMA Enable
#define	HwDCR_FMDE_DIS							~Hw4									// Fly Mode DMA Disable
#define	HwDCR_DMDE_EN							Hw3										// Demand Mode DMA Enable
#define	HwDCR_DMDE_DIS							~Hw3									// Demand Mode DMA Disable
#define	HwDCR_TDR_RUN							Hw2										// TX DMA Run
#define	HwDCR_TDR_STOP							~Hw2									// TX DMA Stop
#define	HwDCR_RDR_RUN							Hw1										// RX DMA Run
#define	HwDCR_RDR_STOP							~Hw1									// RX DMA Stop
#define	HwDCR_DEN_EN							Hw0										// DMA Enable
#define	HwDCR_DEN_DIS							~Hw0									// DMA Disable
                                        	
#define	HwDTCR									*(volatile unsigned long *)0xF0010044	// DMA Transfer Counter Register (Byte unit)
                                        	
#define	HwDFCR									*(volatile unsigned long *)0xF0010048	// DMA FIFO Counter Register (Byte unit)
                                        	
#define	HwDTTCR1								*(volatile unsigned long *)0xF001004C	// Lower-Half of DMA Total Transfer Counter Register
                                        	
#define	HwDTTCR2								*(volatile unsigned long *)0xF0010050	// Upper-Half of DMA Total Transfer Counter Register
                                        	
#define	HwEP0BUF								*(volatile unsigned long *)0xF0010060	// EP0 Buffer Register
                                        	
#define	HwEP1BUF								*(volatile unsigned long *)0xF0010064	// EP1 Buffer Register
                                        	
#define	HwEP2BUF								*(volatile unsigned long *)0xF0010068	// EP2 Buffer Register
                                        	
#define	HwEP3BUF								*(volatile unsigned long *)0xF001006C	// EP3 Buffer Register
                                        	
#define	HwDLYCTRL								*(volatile unsigned long *)0xF0010080	// Delay Control Register
                                        	
#define HwDMAR1									*(volatile unsigned long *)0xF00100A0	// DMA MCU Address Register 1
                                        	
#define HwDMAR2									*(volatile unsigned long *)0xF00100A4	// DMA MCU Address Register 2
                                        	
#define HwDTSR									*(volatile unsigned long *)0xF00100C0	// DMA Transfer Status Register
                                        	
#define	HwUBCFG									*(volatile unsigned long *)0xF00100C4	// R/W, USB Configuration Register
#define HwUBCFG_XSEL_FS							Hw13									// FS Transceiver enable
#define HwUBCFG_TERM_FSOS						(Hw12+Hw11)								// Full-speed termination is enabled for FS-only and FS-Serial modes
#define HwUBCFG_TERM_LS							Hw12									// Low-speed signaling is enable for LS-Serial modes
#define HwUBCFG_TERM_FS							Hw11									// Full-speed termination is enabled
#define HwUBCFG_TERM_HS							HwZERO									// High-speed termination is enabled
#define	HwUBCFG_FSXO_SERIAL						Hw10									// Serial Interface Select
#define	HwUBCFG_DWS_HOST						Hw6										// Host Mode
#define	HwUBCFG_XO_EN							Hw5										// XO_OUT output enable
#define	HwUBCFG_CKSEL_12						HwZERO									// 12MHz
#define	HwUBCFG_CKSEL_24						Hw0										// 24MHz
#define	HwUBCFG_CKSEL_48						Hw1										// 48MHz

/************************************************************************
*	USB Host Register Define					(Base Addr = 0xF0020000)
************************************************************************/
#define	HwHcRevision							*(volatile unsigned long *)0xF0020000	// Control and status register
                                        	
#define	HwHcControl								*(volatile unsigned long *)0xF0020004	// Control and status register
                                        	
#define	HwHcCommandStatus						*(volatile unsigned long *)0xF0020008	// Control and status register
                                        	
#define	HwHcInterruptStatus						*(volatile unsigned long *)0xF002000C	// Control and status register
                                        	
#define	HwHcInterruptEnable						*(volatile unsigned long *)0xF0020010	// Control and status register
                                        	
#define	HwHcInterruptDisable					*(volatile unsigned long *)0xF0020014	// Control and status register
                                        	
#define	HwHcHCCA								*(volatile unsigned long *)0xF0020018	// Memory pointer register
                                        	
#define	HwHcPeroidCurrentED						*(volatile unsigned long *)0xF002001C	// Memory pointer register
                                        	
#define	HwHcControlHeadED						*(volatile unsigned long *)0xF0020020	// Memory pointer register
                                        	
#define	HwHcControlCurrentED					*(volatile unsigned long *)0xF0020024	// Memory pointer register
                                        	
#define	HwHcBulkHeadED							*(volatile unsigned long *)0xF0020028	// Memory pointer register
                                        	
#define	HwHcBulkCurrentED						*(volatile unsigned long *)0xF002002C	// Memory pointer register
                                        	
#define	HwHcDoneHead							*(volatile unsigned long *)0xF0020030	// Memory pointer register
                                        	
#define	HwHcRmInterval							*(volatile unsigned long *)0xF0020034	// Frame counter register
                                        	
#define	HwHcFmRemaining							*(volatile unsigned long *)0xF0020038	// Frame counter register
                                        	
#define	HwHcFmNumber							*(volatile unsigned long *)0xF002003C	// Frame counter register
                                        	
#define	HwHcPeriodStart							*(volatile unsigned long *)0xF0020040	// Frame counter register
                                        	
#define	HwHcLSThreshold							*(volatile unsigned long *)0xF0020044	// Frame counter register
                                        	
#define	HwRhDescriptorA							*(volatile unsigned long *)0xF0020048	// Root hub register
                                        	
#define	HwRhDescriptorB							*(volatile unsigned long *)0xF002004C	// Root hub register
                                        	
#define	HwRhStatus								*(volatile unsigned long *)0xF0020050	// Root hub register
                                        	
#define	HwRhPortStatus1							*(volatile unsigned long *)0xF0020054	// Root hub register
                                        	
#define	HwRhPortStatus2							*(volatile unsigned long *)0xF0020058	// Root hub register
                                        	
#define	HwUHINT_ST								HwHcInterruptStatus
#define	HwUHINT_EN								HwHcInterruptEnable
#define	HwUHINT_DIS								HwHcInterruptDisable
#define	HwUH_RHP0								HwRhPortStatus1
#define	HwUHCMD_ST								HwHcCommandStatus

/************************************************************************
*	IDE Interface Register Define				(Base Addr = 0xF0030000)
************************************************************************/
#define	HwCS0n									*(volatile unsigned long *)0xF0030000	// R/W, PIO CS0n Access register
#define	HwCS00									0xF0030000								// PIO CS00 Register Address
                                        	
#define	REG_PTR    								*(volatile unsigned short *)			// get the content of pointer
#define	IDE_BASE_CS0							0xF0030000
#define	HwIDE_RD_DATA							(REG_PTR(IDE_BASE_CS0+(0x00<<2)+ 0x00))
#define	HwIDE_WR_DATA							HwIDE_RD_DATA
                                        	
#define	HwCS1n									*(volatile unsigned long *)0xF0030020	// R/W, PIO CS1n Access register
#define	HwCS10									0xF0030020								// PIO CS10 Register Address
                                        	
#define	HwPIOCTRL								*(volatile unsigned long *)0xF0030040	// R/W, PIO Mode control register
#define	HwPIOCTRL_SYNC_BYPASS					HwZERO									// Bypass
#define	HwPIOCTRL_SYNC_1						Hw21									// 1 Sync
#define	HwPIOCTRL_SYNC_2						Hw22									// 2 Sync
#define	HwPIOCTRL_MD_PIO						HwZERO									// PIO Mode
#define	HwPIOCTRL_MD_UDMA						Hw20									// UDMA(IN/OUT) Mode
#define	HwPIOCTRL_RDY_IRR						HwZERO									// PW cycles is irrelative of IORDY
#define	HwPIOCTRL_RDY_EXT						Hw0										// PW cycles are extended by IORDY
                                        	
#define	HwUDMACTRL								*(volatile unsigned long *)0xF0030044	// R/W, UDMA Mode control register
#define	HwUDMACTRL_HTRL4						HwZERO									// 4
#define	HwUDMACTRL_HTRL8						Hw28									// 8
#define	HwUDMACTRL_HTRL12						Hw29									// 12
#define	HwUDMACTRL_HTRL14						(Hw29+Hw28)								// 14
#define	HwUDMACTRL_OTL1							HwZERO									// Single Transfer (1read/1write)
#define	HwUDMACTRL_OTL4							Hw25									// 4 (vcnt <= 12)
#define	HwUDMACTRL_OTL8							Hw26									// 8 (vcnt <= 8)
#define	HwUDMACTRL_OTL12						(Hw26+Hw25)								// 12 (vcnt <= 4)
#define	HwUDMACTRL_OTL16						(Hw27+Hw26)								// 16 (Empty)