📄 tcc78xphysical.h
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/************************************************************************
* LCD System Interface Register Define (Base Addr = 0xF0000400)
************************************************************************/
#define HwLCDSICTRL0 *(volatile unsigned long *)0xF0000400 // R/W, Control Register for LCDSI
#define HwLCDSICTRL0_IA_LOW Hw15 // LACBIAS(Data Enable) signal is active low
#define HwLCDSICTRL0_IVS_LOW Hw14 // LYSYNC signal is active low
#define HwLCDSICTRL0_CS_1 Hw7 // If IM is high, CS1 is active during operationgs. Otherwise, it is no applicable. These bits are only available when IM is high
#define HwLCDSICTRL0_RSP_HIGH Hw6 // If IM is high, RS is high. Otherwise, it is not applicable
#define HwLCDSICTRL0_FMT_8RGB565 HwZERO // LCDC pixel data output:RGB565
// LCDSI pixel data output(8bits):RGB565[7:0], RGB565[15:8]
// LCDSI CTRL1-4.WBW must be 1
#define HwLCDSICTRL0_FMT_16RGB565 (Hw4+Hw3) // LCDC pixel data output:RGB565
// LCDSI pixel data output(16bits):RGB565[15:0]
// LCDSI CTRL1-4.WBW must be 0
#define HwLCDSICTRL0_FMT_8RGB888 Hw2 // LCDC pixel data output:RGB888
// LCDSI pixel data output(8bits):R[7:0],G[7:0],B[7:0]
// LCDSI CTRL1-4.WBW must be 1
#define HwLCDSICTRL0_FMT_9RGB888 (Hw3+Hw2) // LCDC pixel data output:RGB888
// LCDSI pixel data output(9bits):{G[2:0],R[5:0]},{B[5:0],G[5:3]}
// LCDSI CTRL1-4.WBW must be 0
#define HwLCDSICTRL0_FMT_16RGB888 (Hw4+Hw2) // LCDC pixel data output:RGB888
// LCDSI pixel data output(16bits):RGB565[15:0]
// LCDSI CTRL1-4.WBW must be 0
#define HwLCDSICTRL0_FMT_18RGB888 (Hw4+Hw3+Hw2) // LCDC pixel data output:RGB888
// LCDSI pixel data output(16bits):{B[3:0],G[5:0],R[5:0]},B[5:4]
// LCDSI CTRL1-4.WBW must be 0
#define HwLCDSICTRL0_OM Hw1 //
#define HwLCDSICTRL0_IM Hw0 //
#define HwLCDSICTRL1 *(volatile unsigned long *)0xF0000800 // R/W, Control Register for nCS0 when RS = 0
#define HwLCDSICTRL1_BW_8 HwZERO // Data width is 8 bits
#define HwLCDSICTRL1_BW_16 Hw15 // Data width is 16 bits
#define HwLCDSICTRL1_BW_18 (Hw31+Hw15) // Data width is 18 bits
#define HwLCDSICTRL2 *(volatile unsigned long *)0xF0000804 // R/W, Control Register for nCS0 when RS = 1
#define HwLCDSICTRL2_BW_8 HwZERO // Data width is 8 bits
#define HwLCDSICTRL2_BW_16 Hw15 // Data width is 16 bits
#define HwLCDSICTRL2_BW_18 (Hw31+Hw15) // Data width is 18 bits
#define HwLCDSICTRL3 *(volatile unsigned long *)0xF0000808 // R/W, Control Register for nCS1 when RS = 0
#define HwLCDSICTRL3_BW_8 HwZERO // Data width is 8 bits
#define HwLCDSICTRL3_BW_16 Hw15 // Data width is 16 bits
#define HwLCDSICTRL3_BW_18 (Hw31+Hw15) // Data width is 18 bits
#define HwLCDSICTRL4 *(volatile unsigned long *)0xF000080C // R/W, Control Register for nCS0 when RS = 1
#define HwLCDSICTRL4_BW_8 HwZERO // Data width is 8 bits
#define HwLCDSICTRL4_BW_16 Hw15 // Data width is 16 bits
#define HwLCDSICTRL4_BW_18 (Hw31+Hw15) // Data width is 18 bits
#define HwLCDSICS0RS0 *(volatile short *)0xF0000810 // R/W, If this register is read or written, reading or writing operations are generated on nCS0 while RS = 0
#define HwLCDSICS0RS1 *(volatile short *)0xF0000818 // R/W, If this register is read or written, reading or writing operations are generated on nCS0 while RS = 1
#define HwLCDSICS1RS0 *(volatile short *)0xF0000820 // R/W, If this register is read or written, reading or writing operations are generated on nCS1 while RS = 0
#define HwLCDSICS1RS1 *(volatile short *)0xF0000828 // R/W, If this register is read or written, reading or writing operations are generated on nCS1 while RS = 1
/*
#define HwLCDSICS0RS0 *(volatile unsigned long *)0xF0000810 // R/W, If this register is read or written, reading or writing operations are generated on nCS0 while RS = 0
#define HwLCDSICS0RS1 *(volatile unsigned long *)0xF0000818 // R/W, If this register is read or written, reading or writing operations are generated on nCS0 while RS = 1
#define HwLCDSICS1RS0 *(volatile unsigned long *)0xF0000820 // R/W, If this register is read or written, reading or writing operations are generated on nCS1 while RS = 0
#define HwLCDSICS1RS1 *(volatile unsigned long *)0xF0000828 // R/W, If this register is read or written, reading or writing operations are generated on nCS1 while RS = 1
*/
#define HwLCDSICTRL5 *(volatile unsigned long *)0xF0000830 // R/W,
#define HwLCDSICTRL5_WBW Hw31 //
#define HwLCDSICTRL6 *(volatile unsigned long *)0xF0000834 // R/W,
#define HwLCDSICTRL6_WBW Hw31 //
#define HwLCDSICTRL7 *(volatile unsigned long *)0xF0000838 // R/W,
#define HwLCDSICTRL7_WBW Hw31 //
#define HwLCDSICTRL8 *(volatile unsigned long *)0xF000083C // R/W,
#define HwLCDSICTRL8_WBW Hw31 //
/***********************************************************************
* USB Controller Register Define (Base Addr = 0xF0010000)
************************************************************************/
#define HwIR *(volatile unsigned long *)0xF0010000 // R/W, Index Register
#define HwEIR *(volatile unsigned long *)0xF0010004 // R/W, Endpoint Interrupt Register
#define HwEIR_EP0INT Hw0 // W : Clear the EP0 interrupt flag, R : Indicates that the USB EP0 interrupt has been generated
#define HwEIR_EP1INT Hw1 // W : Clear the EP1 interrupt flag, R : Indicates that the USB EP1 interrupt has been generated
#define HwEIR_EP2INT Hw2 // W : Clear the EP2 interrupt flag, R : Indicates that the USB EP2 interrupt has been generated
#define HwEIR_EP3INT Hw3 // W : Clear the EP3 interrupt flag, R : Indicates that the USB EP3 interrupt has been generated
#define HwEIER *(volatile unsigned long *)0xF0010008 // R/W, Endpoint Interrupt Enable Register
#define HwEIER_EP0INT_EN Hw0 // Enable EP0 interrupt
#define HwEIER_EP0INT_DIS ~Hw0 // Disable EP0 interrupt
#define HwEIER_EP1INT_EN Hw1 // Enable EP1 interrupt
#define HwEIER_EP1INT_DIS ~Hw1 // Disable EP1 interrupt
#define HwEIER_EP2INT_EN Hw2 // Enable EP2 interrupt
#define HwEIER_EP2INT_DIS ~Hw2 // Disable EP2 interrupt
#define HwEIER_EP3INT_EN Hw3 // Enable EP3 interrupt
#define HwEIER_EP3INT_DIS ~Hw3 // Disable EP3 interrupt
#define HwFAR *(volatile unsigned long *)0xF001000C // Function Address Register
#define HwEDR *(volatile unsigned long *)0xF0010014 // R/W, Endpoint Direction Register
#define HwEDR_EP0_TX Hw0 // Tx Endpoint
#define HwEDR_EP0_RX ~Hw0 // Rx Endpoint
#define HwEDR_EP1_TX Hw1 // Tx Endpoint
#define HwEDR_EP1_RX ~Hw1 // Rx Endpoint
#define HwEDR_EP2_TX Hw2 // Tx Endpoint
#define HwEDR_EP2_RX ~Hw2 // Rx Endpoint
#define HwEDR_EP3_TX Hw3 // Tx Endpoint
#define HwEDR_EP3_RX ~Hw3 // Rx Endpoint
#define HwUTST *(volatile unsigned long *)0xF0010018 // Test Register
#define HwUTST_VBUS_ON Hw15 //
#define HwUTST_VBUS_OFF ~Hw15 //
#define HwUTST_EUERR Hw13 // EB underrun error in transceiver
#define HwUTST_PERR Hw12 // PID Error Flag
#define HwUTST_TPS_ON Hw3 // Transmit test packets
#define HwUTST_TPS_OFF ~Hw3 // Stop Transmitting
#define HwUTST_TKS_ON Hw2 // Transmit test K packets
#define HwUTST_TKS_OFF ~Hw2 // Stop Transmitting
#define HwUTST_TJS_ON Hw1 // Transmit test J packets
#define HwUTST_TJS_OFF ~Hw1 // Stop Transmitting
#define HwUTST_TSNS_ON Hw0 // Transmit test SE0 NAK
#define HwUTST_TSNS_OFF ~Hw0 // Stop Transmitting
#define HwSSR *(volatile unsigned long *)0xF001001C // R/W, System Status Register
#define HwSSR_BAERR Hw15 // Byte-Align Error
#define HwSSR_TMERR Hw14 // Timeout Error
#define HwSSR_BSERR Hw13 // Bit Stuff Error
#define HwSSR_TCERR Hw12 // Token CRC Error
#define HwSSR_DCERR Hw11 // Data CRC Error
#define HwSSR_EOERR Hw10 // EB Overrun Error
#define HwSSR_VBUS_OFF Hw9 // VBUS is in Off state.
// (active when VBUS OFF interrupt is enabled)
#define HwSSR_VBUS_ON Hw8 // VBUS is in ON state.
// (active when VBUS ON interrupt is enabled)
#define HwSSR_TBM Hw7 // Toggle Bit Mismatch Error
#define HwSSR_DP_HIGH Hw6 // D+ == High State
#define HwSSR_DP_LOW ~Hw6 // D+ == Low State
#define HwSSR_DN_HIGH Hw5 // D- == High State
#define HwSSR_DN_LOW ~Hw5 // D- == Low State
#define HwSSR_HSP_HIGH Hw4 // Host is High Speed.
#define HwSSR_HSP_FULL ~Hw4 // Host is Full Speed.
#define HwSSR_SDE_END Hw3 // Speed Detection is Ended.
#define HwSSR_HFRM Hw2 // Host sends Resume signaling.
#define HwSSR_HFSUSP Hw1 // Host sends Suspend signaling.
#define HwSSR_HFRES Hw0 // Host sends Reset signaling.
#define HwSCR *(volatile unsigned long *)0xF0010020 // R/W, System Control Register
#define HwSCR_DTZIEN_EN Hw14 // DMA Total Count Zero Interrupt Enabled
#define HwSCR_DTZIEN_DIS ~Hw14 // DMA Total Count Zero Interrupt Disabled
#define HwSCR_DIEN_EN Hw12 // Dual Interrupt Enabled
#define HwSCR_DIEN_DIS ~Hw12 // Dual Interrupt Disabled
#define HwSCR_VBUSOFF_EN Hw11 // HwSSR(VBUS OFF flag) Enabled
#define HwSCR_VBUSOFF_DIS ~Hw11 // HwSSR(VBUS OFF flag) Disabled
#define HwSCR_VBUSON_EN Hw10 // HwSSR(VBUS ON flag) Enabled
#define HwSCR_VBUSON_DIS ~Hw10 // HwSSR(VBUS ON flag) Disabled
#define HwSCR_RWDE_EN Hw9 // High byte data [15:8] is sent first.
#define HwSCR_RWDE_DIS ~Hw9 // Low byte data [7:0] is sent first.
#define HwSCR_EIE_EN Hw8 // Error Interrupt Enable
#define HwSCR_EIE_DIS ~Hw8 // Error Interrupt Disable
#define HwSCR_SDE_EN Hw6 // Speed Detection End Interrupt Enable
#define HwSCR_SDE_DIS ~Hw6 // Speed Detection End Interrupt Disable
#define HwSCR_RRDE_EN Hw5 // First received data is loaded in Low byte [7:0]
#define HwSCR_RRDE_DIS ~Hw5 // First received data is loaded in High byte [15:8]
#define HwSCR_IPS_HIGH Hw4 // Active High Interrupt Polarity
#define HwSCR_IPS_LOW ~Hw4 // Active Low Interrupt Polarity
#define HwSCR_MFRM_ON Hw2 // USB Core generates Resume signaling.
#define HwSCR_MFRM_OFF ~Hw2 // USB Core stop generating Resume signaling.
#define HwSCR_HSUSPE_EN Hw1 // USB Core can repond to the Suspend signaling from HOST.
#define HwSCR_HSUSPE_DIS ~Hw1 // USB Core cannot repond to the Suspend signaling from HOST.
#define HwSCR_HRESE_EN Hw0 // USB Core can repond to the Reset signaling from HOST.
#define HwSCR_HRESE_DIS ~Hw0 // USB Core cannot repond to the Reset signaling from HOST.
#define HwEP0SR *(volatile unsigned long *)0xF0010024 // R/W, EP0 Status Register
#define HwEP0SR_LWO Hw6 // Last Word Odd
#define HwEP0SR_SHT Hw4 // Stall Handshake Transmitted
#define HwEP0SR_TST Hw1 // TX Successfully Transmitted
#define HwEP0SR_RSR Hw0 // RX Successfully Received
#define HwEP0CR *(volatile unsigned long *)0xF0010028 // R/W, EP0 Control Register
#define HwEP0CR_TTE_EN Hw3 // TX Test Enable
#define HwEP0CR_TTE_DIS ~Hw3 // TX Test Disable
#define HwEP0CR_TTS_SET Hw2 // Set Toggle Bit (active when TTE is set)
#define HwEP0CR_TTS_CLR ~Hw2 // Clear Toggle Bit (active when TTE is set)
#define HwEP0CR_ESS_SET Hw1 // Send STALL Handshake to Host
#define HwEP0CR_ESS_CLR ~Hw1 // Stop sending STALL Handshake
#define HwEP0CR_TZLS_SET Hw0 // Transmit Zero Length Data (active when TTE is set)
#define HwEP0CR_TZLS_CLR ~Hw0 // Stop Transmitting Zero Length Data (active when TTE is set)
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