📄 tcc78xphysical.h
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#define HwLKM1_A11_MAX (Hw25+Hw24) //
#define HwLKM2 *(volatile unsigned long *)0xF0000058 // W, LCD Keying Mask Register 2
#define HwLKM2_A21_MAX (Hw25+Hw24) //
#define HwLDS *(volatile unsigned long *)0xF000005C // W, LCD Display Size Register
#define HwLSTATUS *(volatile unsigned long *)0xF0000060 // R/Clr, LCD Status Register
#define HwLSTATUS_VS Hw15 // Monitoring vertical sync.
#define HwLSTATUS_ITY Hw12 // Interrupt Type
#define HwLSTATUS_ICR Hw8 // Interrupt Clear, using ITY is level type
#define HwLSTATUS_BY Hw6 // Busy signal
#define HwLSTATUS_EF Hw5 // Even-Field(Read Only). 0:Odd field or frame, 1:Even field or frame
#define HwLSTATUS_DD Hw4 // Disable Done(Read/Clear). If LEN is disabled, DD will be 1 after current frame has been displayed. As MDD of LIM register is cleared, it can be LCD interrupt source
#define HwLSTATUS_RU Hw3 // Register Update(Read/Clear). It indicates that all registers programmed are applied to current frame data. As MRU of LIM register is cleared, it can be LCD interrupt source
#define HwLSTATUS_FU Hw0 // FIFO underrun(Read/Clear). It indicates that FIFO underrun has been occurred. In this case, LCLK frequency must be lower. As MFU of LIM register is cleared, it can be LCD interrupt source
#define HwLIM *(volatile unsigned long *)0xF0000064 // W, LCD Interrupt Register
#define HwLIM_MDD Hw4 // Masking disable done interrupt
#define HwLIM_MRU Hw3 // Masking register update interrupt
#define HwLIM_MFU Hw0 // Masking FIFO underrun interrupt
#define HwLI0C *(volatile unsigned long *)0xF0000068 // W, LCD Image 0 Control Register
#define HwLIOC_IMG012 HwZERO //
#define HwLIOC_IMG021 Hw12 //
#define HwLIOC_IMG102 Hw13 //
#define HwLIOC_IMG201 (Hw13+Hw12) //
#define HwLIOC_IMG120 Hw14 //
#define HwLIOC_IMG210 (Hw14+Hw12) //
#define HwLI0C_BR_BE Hw7 // Big Endian pixel data
#define HwLI0C_YUV_420 Hw4 // YUV 4:2:0
#define HwLI0C_YUV_422 (Hw5+Hw4) // YUV 4:2:2
#define HwLI0C_YUV_422P (Hw6+Hw5+Hw4) // YUV 4:2:2 Patch
#define HwLI0C_BPP_1 HwZERO // Bit Per Pixel = 1bpp
#define HwLI0C_BPP_2 Hw0 // Bit Per Pixel = 2bpp
#define HwLI0C_BPP_4 Hw1 // Bit Per Pixel = 4bpp
#define HwLI0C_BPP_332 (Hw1+Hw0) // Bit Per Pixel = 332bpp
#define HwLI0C_BPP_444 Hw2 // Bit Per Pixel = 444bpp
#define HwLI0C_BPP_565 (Hw2+Hw0) // Bit Per Pixel = 565bpp
#define HwLI0C_BPP_555 (Hw2+Hw1) // Bit Per Pixel = 555bpp
#define HwLI0C_BPP_888 (Hw2+Hw1+Hw0) // Bit Per Pixel = 888bpp
#define HwLI0P *(volatile unsigned long *)0xF000006C // W, LCD Image 0 Position Register
#define HwLI0S *(volatile unsigned long *)0xF0000070 // W, LCD Image 0 Size Register
#define HwLI0BA0 *(volatile unsigned long *)0xF0000074 // W, LCD Image 0 Base Address 0 Register
#define HwLI0CA *(volatile unsigned long *)0xF0000078 // W, LCD Image 0 Current Address Register
#define HwLI0BA1 *(volatile unsigned long *)0xF000007C // W, LCD Image 0 Base Address 1 Register
#define HwLI0BA2 *(volatile unsigned long *)0xF0000080 // W, LCD Image 0 Base Address 2 Register
#define HwLI0O *(volatile unsigned long *)0xF0000084 // W, LCD Image 0 Offset Register
#define HwLI0SCALE *(volatile unsigned long *)0xF0000088 // W, LCD Image 0 Scale Ratio
#define HwLI0SCALE_Y_NS HwZERO // Non-Scalable
#define HwLI0SCALE_Y_D2 Hw4 // DownScale by 2
#define HwLI0SCALE_Y_D3 Hw5 // DownScale by 3
#define HwLI0SCALE_Y_D4 (Hw5+Hw4) // DownScale by 4
#define HwLI0SCALE_Y_D8 (Hw6+Hw5+Hw4) // DownScale by 8
#define HwLI0SCALE_Y_U2 (Hw7+Hw4) // UpScale by 2
#define HwLI0SCALE_Y_U3 (Hw7+Hw5) // UpScale by 3
#define HwLI0SCALE_Y_U4 (Hw7+Hw5+Hw4) // UpScale by 4
#define HwLI0SCALE_Y_U8 (Hw7+Hw6+Hw5+Hw4) // UpScale by 8
#define HwLI0SCALE_X_NS HwZERO // Non-Scalable
#define HwLI0SCALE_X_D2 Hw0 // DownScale by 2
#define HwLI0SCALE_X_D3 Hw1 // DownScale by 3
#define HwLI0SCALE_X_D4 (Hw1+Hw0) // DownScale by 4
#define HwLI0SCALE_X_D8 (Hw2+Hw1+Hw0) // DownScale by 8
#define HwLI0SCALE_X_U2 (Hw3+Hw0) // UpScale by 2
#define HwLI0SCALE_X_U3 (Hw3+Hw1) // UpScale by 3
#define HwLI0SCALE_X_U4 (Hw3+Hw1+Hw0) // UpScale by 4
#define HwLI0SCALE_X_U8 (Hw3+Hw2+Hw1+Hw0) // UpScale by 8
#define HwLI1C *(volatile unsigned long *)0xF000008C // W, LCD Image 1 Control Register
#define HwLI1C_BR_BE Hw7 // Big Endian pixel data
#define HwLI1C_YUV_420 Hw4 // YUV 4:2:0
#define HwLI1C_YUV_422 (Hw5+Hw4) // YUV 4:2:2
#define HwLI1C_YUV_422P (Hw6+Hw5+Hw4) // YUV 4:2:2 Patch
#define HwLI1C_BPP_1 HwZERO // Bit Per Pixel = 1bpp
#define HwLI1C_BPP_2 Hw0 // Bit Per Pixel = 2bpp
#define HwLI1C_BPP_4 Hw1 // Bit Per Pixel = 4bpp
#define HwLI1C_BPP_332 (Hw1+Hw0) // Bit Per Pixel = 332bpp
#define HwLI1C_BPP_444 Hw2 // Bit Per Pixel = 444bpp
#define HwLI1C_BPP_565 (Hw2+Hw0) // Bit Per Pixel = 565bpp
#define HwLI1C_BPP_555 (Hw2+Hw1) // Bit Per Pixel = 555bpp
#define HwLI1C_BPP_888 (Hw2+Hw1+Hw0) // Bit Per Pixel = 888bpp
#define HwLI1P *(volatile unsigned long *)0xF0000090 // W, LCD Image 1 Position Register
#define HwLI1S *(volatile unsigned long *)0xF0000094 // W, LCD Image 1 Size Register
#define HwLI1BA0 *(volatile unsigned long *)0xF0000098 // W, LCD Image 1 Base Address 0 Register
#define HwLI1CA *(volatile unsigned long *)0xF000009C // W, LCD Image 1 Current Address Register
#define HwLI1BA1 *(volatile unsigned long *)0xF00000A0 // W, LCD Image 1 Base Address 1 Register
#define HwLI1BA2 *(volatile unsigned long *)0xF00000A4 // W, LCD Image 1 Base Address 2 Register
#define HwLI1O *(volatile unsigned long *)0xF00000A8 // W, LCD Image 1 Offset Register
#define HwLI1SCALE *(volatile unsigned long *)0xF00000AC // W, LCD Image 1 Scale Ratio
#define HwLI1SCALE_Y_NS HwZERO // Non-Scalable
#define HwLI1SCALE_Y_D2 Hw4 // DownScale by 2
#define HwLI1SCALE_Y_D3 Hw5 // DownScale by 3
#define HwLI1SCALE_Y_D4 (Hw5+Hw4) // DownScale by 4
#define HwLI1SCALE_Y_D8 (Hw6+Hw5+Hw4) // DownScale by 8
#define HwLI1SCALE_Y_U2 (Hw7+Hw4) // UpScale by 2
#define HwLI1SCALE_Y_U3 (Hw7+Hw5) // UpScale by 3
#define HwLI1SCALE_Y_U4 (Hw7+Hw5+Hw4) // UpScale by 4
#define HwLI1SCALE_Y_U8 (Hw7+Hw6+Hw5+Hw4) // UpScale by 8
#define HwLI1SCALE_X_NS HwZERO // Non-Scalable
#define HwLI1SCALE_X_D2 Hw0 // DownScale by 2
#define HwLI1SCALE_X_D3 Hw1 // DownScale by 3
#define HwLI1SCALE_X_D4 (Hw1+Hw0) // DownScale by 4
#define HwLI1SCALE_X_D8 (Hw2+Hw1+Hw0) // DownScale by 8
#define HwLI1SCALE_X_U2 (Hw3+Hw0) // UpScale by 2
#define HwLI1SCALE_X_U3 (Hw3+Hw1) // UpScale by 3
#define HwLI1SCALE_X_U4 (Hw3+Hw1+Hw0) // UpScale by 4
#define HwLI1SCALE_X_U8 (Hw3+Hw2+Hw1+Hw0) // UpScale by 8
#define HwLI2C *(volatile unsigned long *)0xF00000B0 // W, LCD Image 2 Control Register
#define HwLI2C_LUT_EN Hw9 // Use the Color Lookup Table
#define HwLI2C_BR_BE Hw7 // Big Endian pixel data
#define HwLI2C_YUV_420 Hw4 // YUV 4:2:0
#define HwLI2C_YUV_422 (Hw5+Hw4) // YUV 4:2:2
#define HwLI2C_YUV_422P (Hw6+Hw5+Hw4) // YUV 4:2:2 Patch
#define HwLI2C_BPP_1 HwZERO // Bit Per Pixel = 1bpp
#define HwLI2C_BPP_2 Hw0 // Bit Per Pixel = 2bpp
#define HwLI2C_BPP_4 Hw1 // Bit Per Pixel = 4bpp
#define HwLI2C_BPP_332 (Hw1+Hw0) // Bit Per Pixel = 332bpp
#define HwLI2C_BPP_444 Hw2 // Bit Per Pixel = 444bpp
#define HwLI2C_BPP_565 (Hw2+Hw0) // Bit Per Pixel = 565bpp
#define HwLI2C_BPP_555 (Hw2+Hw1) // Bit Per Pixel = 555bpp
#define HwLI2C_BPP_888 (Hw2+Hw1+Hw0) // Bit Per Pixel = 888bpp
#define HwLI2P *(volatile unsigned long *)0xF00000B4 // W, LCD Image 2 Position Register
#define HwLI2S *(volatile unsigned long *)0xF00000B8 // W, LCD Image 2 Size Register
#define HwLI2BA0 *(volatile unsigned long *)0xF00000BC // W, LCD Image 2 Base Address 0 Register
#define HwLI2CA *(volatile unsigned long *)0xF00000C0 // W, LCD Image 2 Current Address Register
#define HwLI2BA1 *(volatile unsigned long *)0xF00000C4 // W, LCD Image 2 Base Address 1 Register
#define HwLI2BA2 *(volatile unsigned long *)0xF00000C8 // W, LCD Image 2 Base Address 2 Register
#define HwLI2O *(volatile unsigned long *)0xF00000CC // W, LCD Image 2 Offset Register
#define HwLI2SCALE *(volatile unsigned long *)0xF00000D0 // W, LCD Image 2 Scale Ratio
#define HwLI2SCALE_Y_NS HwZERO // Non-Scalable
#define HwLI2SCALE_Y_D2 Hw4 // DownScale by 2
#define HwLI2SCALE_Y_D3 Hw5 // DownScale by 3
#define HwLI2SCALE_Y_D4 (Hw5+Hw4) // DownScale by 4
#define HwLI2SCALE_Y_D8 (Hw6+Hw5+Hw4) // DownScale by 8
#define HwLI2SCALE_Y_U2 (Hw7+Hw4) // UpScale by 2
#define HwLI2SCALE_Y_U3 (Hw7+Hw5) // UpScale by 3
#define HwLI2SCALE_Y_U4 (Hw7+Hw5+Hw4) // UpScale by 4
#define HwLI2SCALE_Y_U8 (Hw7+Hw6+Hw5+Hw4) // UpScale by 8
#define HwLI2SCALE_X_NS HwZERO // Non-Scalable
#define HwLI2SCALE_X_D2 Hw0 // DownScale by 2
#define HwLI2SCALE_X_D3 Hw1 // DownScale by 3
#define HwLI2SCALE_X_D4 (Hw1+Hw0) // DownScale by 4
#define HwLI2SCALE_X_D8 (Hw2+Hw1+Hw0) // DownScale by 8
#define HwLI2SCALE_X_U2 (Hw3+Hw0) // UpScale by 2
#define HwLI2SCALE_X_U3 (Hw3+Hw1) // UpScale by 3
#define HwLI2SCALE_X_U4 (Hw3+Hw1+Hw0) // UpScale by 4
#define HwLI2SCALE_X_U8 (Hw3+Hw2+Hw1+Hw0) // UpScale by 8
#define HwDLCTRL *(volatile unsigned long *)0xF000000D4 // W, Dual LCD Control
#define HwDLCTRL_DRE Hw4 // Dual LCD Register Update Enable
#define HwDLCTRL_DLE Hw0 // Dual LCD Operation Enable
#define HwDLCSA0 *(volatile unsigned long *)0xF00000DC // W, Dual LCD Configuration Start Address 0
#define HwDLCSA1 *(volatile unsigned long *)0xF00000E0 // W, Dual LCD Configuration Start Address 1
#define HwY2RP0 *(volatile unsigned long *)0xF00000E4 // W, YCbCr to RGB Conversion Parameter 0
#define HwY2RP1 *(volatile unsigned long *)0xF00000E8 // W, YCbCr to RGB Conversion Parameter 1
#define HwLCDLUT *(volatile unsigned long *)0xF0000C00 // W, LCD Lookup Table
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