📄 tcc79x_physical.h
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#define HwEP0CR_TTS_SET Hw2 // Set Toggle Bit (active when TTE is set)
#define HwEP0CR_TTS_CLR ~Hw2 // Clear Toggle Bit (active when TTE is set)
#define HwEP0CR_ESS_SET Hw1 // Send STALL Handshake to Host
#define HwEP0CR_ESS_CLR ~Hw1 // Stop sending STALL Handshake
#define HwEP0CR_TZLS_SET Hw0 // Transmit Zero Length Data (active when TTE is set)
#define HwEP0CR_TZLS_CLR ~Hw0 // Stop Transmitting Zero Length Data (active when TTE is set)
#define HwESR *(volatile unsigned long *)0xF001002C // R/W, Endpoint Status Register
#define HwESR_FUDR Hw15 // FIFO Underflow
#define HwESR_FOVF Hw14 // FIFO Overflow
#define HwESR_FPID_ON Hw11 // First OUT packet cannot generate interrupt in OUT DMA operation.
#define HwESR_FPID_OFF ~Hw11 // First OUT packet generate interrupt in OUT DMA operation.
#define HwESR_OSD Hw10 // OUT packet is first received after DMA registers are set.
#define HwESR_DTCZ Hw9 // DMA Total Count Zero
#define HwESR_SPT Hw8 // Short Packet Received during OUT DMA operation
#define HwESR_DOM Hw7 // Dual Operation Mode (Max packet = FIFO size / 2)
#define HwESR_FFS Hw6 // FIFO Flushed (Cleared by FLUSH of HwECR register)
#define HwESR_FSC Hw5 // Function Stall Condition is sent to Host.
#define HwESR_LWO Hw4 // Last Word Odd
#define HwESR_PSIF_NP HwZERO // No Packet in FIFO
#define HwESR_PSIF_1P Hw2 // 1 Packet in FIFO
#define HwESR_PSIF_2P Hw3 // 2 Packets in FIFO
#define HwESR_TPS Hw1 // TX Packet Success
#define HwESR_RPS Hw0 // RX Packet Success
#define HwECR *(volatile unsigned long *)0xF0010030 // R/W, Endpoint Control Register
#define HwECR_INHLD_EN Hw12 // In-Packet Hold Enable (USB sends NAK regardless of IN FIFO status)
#define HwECR_INHLD_DIS ~Hw12 // In-Packet Hold Disable (USB sends IN data)
#define HwECR_OUTHLD_EN Hw11 // Out-Packet Hold Enable (USB doesn't accept OUT data)
#define HwECR_OUTHLD_DIS ~Hw11 // Out-Packet Hold Disable (USB accept OUT data)
#define HwECR_TNPMF_1T Hw9 // 1 Transaction Per MicroFrame
#define HwECR_TNPMF_2T Hw10 // 2 Transactions Per MicroFrame
#define HwECR_TNPMF_3T (Hw10+Hw9) // 3 Transactions Per MicroFrame
#define HwECR_DUEN_EN Hw7 // Dual FIFO Mode Enable
#define HwECR_DUEN_DIS ~Hw7 // Dual FIFO Mode Disable
#define HwECR_FLUSH_EN Hw6 // FIFO is Flushed (automatically cleared after writing)
#define HwECR_TTE_EN Hw5 // TX Toggle Forcing Enable
#define HwECR_TTE_DIS ~Hw5 // TX Toggle Forcing Disable
#define HwECR_TTS_PID0 HwZERO // TX Data Toggle bit = PID 0
#define HwECR_TTS_PID1 Hw3 // TX Data Toggle bit = PID 1
#define HwECR_TTS_PID2 Hw4 // TX Data Toggle bit = PID 2 (ISO only)
#define HwECR_TTS_PIDM (Hw4+Hw3) // TX Data Toggle bit = PID M (ISO only)
#define HwECR_CDP_CLR Hw2 // Clear Data PID register
#define HwECR_ESS_SET Hw1 // send STALL handshake to Host
#define HwECR_ESS_CLR ~Hw1 // stop sending STALL handshake
#define HwECR_TZLS_SET Hw0 // Transmit Zero Length Data (active when TTE is set)
#define HwECR_TZLS_CLR ~Hw0 // Stop Transmitting Zero Length Data (active when TTE is set)
#define HwBRCR *(volatile unsigned long *)0xF0010034 // R, Byte Read Counter (Half-word unit)
#define HwBWCR *(volatile unsigned long *)0xF0010038 // W, Byte Write Counter (Byte unit)
#define HwMPR *(volatile unsigned long *)0xF001003C // R/W, Max Packet Register (Byte unit)
#define HwDCR *(volatile unsigned long *)0xF0010040 // R/W, DMA Control Register
#define HwDCR_ARDRD_ON Hw5 // Auto RX DMA Run Disable On
#define HwDCR_ARDRD_OFF ~Hw5 // Auto RX DMA Run Disable Off
#define HwDCR_FMDE_EN Hw4 // Fly Mode DMA Enable
#define HwDCR_FMDE_DIS ~Hw4 // Fly Mode DMA Disable
#define HwDCR_DMDE_EN Hw3 // Demand Mode DMA Enable
#define HwDCR_DMDE_DIS ~Hw3 // Demand Mode DMA Disable
#define HwDCR_TDR_RUN Hw2 // TX DMA Run
#define HwDCR_TDR_STOP ~Hw2 // TX DMA Stop
#define HwDCR_RDR_RUN Hw1 // RX DMA Run
#define HwDCR_RDR_STOP ~Hw1 // RX DMA Stop
#define HwDCR_DEN_EN Hw0 // DMA Enable
#define HwDCR_DEN_DIS ~Hw0 // DMA Disable
#define HwDTCR *(volatile unsigned long *)0xF0010044 // DMA Transfer Counter Register (Byte unit)
#define HwDFCR *(volatile unsigned long *)0xF0010048 // DMA FIFO Counter Register (Byte unit)
#define HwDTTCR1 *(volatile unsigned long *)0xF001004C // Lower-Half of DMA Total Transfer Counter Register
#define HwDTTCR2 *(volatile unsigned long *)0xF0010050 // Upper-Half of DMA Total Transfer Counter Register
#define HwEP0BUF *(volatile unsigned long *)0xF0010060 // EP0 Buffer Register
#define HwEP1BUF *(volatile unsigned long *)0xF0010064 // EP1 Buffer Register
#define HwEP2BUF *(volatile unsigned long *)0xF0010068 // EP2 Buffer Register
#define HwEP3BUF *(volatile unsigned long *)0xF001006C // EP3 Buffer Register
#define HwPLICR *(volatile unsigned long *)0xF00100A0 // PHYLINK Interface Control Register
#define HwPCR *(volatile unsigned long *)0xF00100A4 // PHY Control Register
#define HwPCR_URST_EN Hw7 // uTMI_RESET enable
#define HwPCR_URST_DIS ~Hw7 // UTMI_RESET disable
#define HwPCR_SIDC_1 Hw6 // SIDDQ Control ; SIDDQ = 1
#define HwPCR_SIDC_0 ~Hw6 // SIDDQ Control ; SIDDQ = 0
#define HwPCR_OPMC_RESET ((~Hw5)&(~Hw4)) // OPMODE Control ; reset, reserved
#define HwPCR_OPMC_DIS Hw4 // OPMODE Control ; Disable bit stuffing and NRZI encoding
#define HwPCR_OPMC_ND Hw5 // OPMODE Control ; Non-Driving
#define HwPCR_OPMC_NORMAL (Hw5+Hw4) // OPMODE Control ; Normal
#define HwPCR_TMSC_1 Hw3 // TERMSEL Control ; TERMSEL = 1
#define HwPCR_TMSC_0 ~Hw3 // TERMSEL Control ; TERMSEL = 0
#define HwPCR_XCRC_1 Hw2 // XCVRSEL = 1
#define HwPCR_XCRC_0 ~Hw2 // XCVRSEL = 0
#define HwPCR_SUSPC_1 Hw1 // SUSPENDM = 1
#define HwPCR_SUSPC_0 ~Hw1 // SUSPENDM = 0
#define HwPCR_PCE_EN Hw0 // Control Enable
#define HwPCR_PCE_DIS ~Hw0 // Control Disable
#define HwUPCFG0 *(volatile unsigned long *)0xF00100C8 // USB PHY Configuration Register 0
#define HwUPCFG0_PR_EN Hw14 // Rer-Port Reset Enable
#define HwUPCFG0_PR_DIS ~Hw14 // Rer-Port Reset Disable
#define HwUPCFG0_CM_EN Hw13 // Common Block Power Down Enable
#define HwUPCFG0_CM_DIS ~Hw13 // Common Block Power Down Disable
#define HwUPCFG0_RCS_11 (Hw12+Hw11) // Reference Clock Select for PLL Block ; The PLL uses CLKCORE as reference
#define HwUPCFG0_RCS_10 Hw12 // Reference Clock Select for PLL Block ; The PLL uses CLKCORE as reference
#define HwUPCFG0_RCS_01 Hw11 // Reference Clock Select for PLL Block ; The XO block uses an external clock supplied on the XO pin
#define HwUPCFG0_RCS_00 ((~Hw12)&(~Hw11)) // Reference Clock Select for PLL Block ; The XO block uses the clock from a crystal
#define HwUPCFG0_RCD_48 Hw10 // Reference Clock Frequency Select ; 48MHz
#define HwUPCFG0_RCD_24 Hw9 // Reference Clock Frequency Select ; 24MHz
#define HwUPCFG0_RCD_12 ((~Hw10)&(~Hw9)) // Reference Clock Frequency Select ; 12MHz
#define HwUPCFG0_SDI_EN Hw8 // IDDQ Test Enable ; The analog blocks are powered down
#define HwUPCFG0_SDI_DIS ~Hw8 // IDDQ Test Disable ; The analog blocks are not powered down
#define HwUPCFG0_FO_SI Hw7 // UTMI/Serial Interface Select ; Serial Interface
#define HwUPCFG0_FO_UTMI ~Hw7 // UTMI/Serial Interface Select ; UTMI
#define HwUPCFG1 *(volatile unsigned long *)0xF00100CC // USB PHY Configuration Register 1
#define HwUPCFG2 *(volatile unsigned long *)0xF00100D0 // USB PHY Configuration Register 2
#define HwUPCFG3 *(volatile unsigned long *)0xF00100D4 // USB PHY Configuration Register 3
//#define HwDLYCTRL *(volatile unsigned long *)0xF0010080 // Delay Control Register
//#define HwDMAR1 *(volatile unsigned long *)0xF00100A0 // DMA MCU Address Register 1
//#define HwDMAR2 *(volatile unsigned long *)0xF00100A4 // DMA MCU Address Register 2
//#define HwDTSR *(volatile unsigned long *)0xF00100C0 // DMA Transfer Status Register
//#define HwUBCFG *(volatile unsigned long *)0xF00100C4 // R/W, USB Configuration Register
//#define HwUBCFG_XSEL_FS Hw13 // FS Transceiver enable
//#define HwUBCFG_TERM_FSOS (Hw12+Hw11) // Full-speed termination is enabled for FS-only and FS-Serial modes
//#define HwUBCFG_TERM_LS Hw12 // Low-speed signaling is enable for LS-Serial modes
//#define HwUBCFG_TERM_FS Hw11 // Full-speed termination is enabled
//#define HwUBCFG_TERM_HS HwZERO // High-speed termination is enabled
//#define HwUBCFG_FSXO_SERIAL Hw10 // Serial Interface Select
//#define HwUBCFG_DWS_HOST Hw6 // Host Mode
//#define HwUBCFG_XO_EN Hw5 // XO_OUT output enable
//#define HwUBCFG_CKSEL_12 HwZERO // 12MHz
//#define HwUBCFG_CKSEL_24 Hw0 // 24MHz
//#define HwUBCFG_CKSEL_48 Hw1 // 48MHz
/************************************************************************
* USB Host Register Define (Base Addr = 0xF0020000)
************************************************************************/
#define HwUSBH_BASE *(volatile unsigned long *)0xF0020000 // USB Host Base Register
#define HwHcRevision *(volatile unsigned long *)0xF0020000 // Control and status register
#define HwHcControl *(volatile unsigned long *)0xF0020004 // Control and status register
#define HwHcCommandStatus *(volatile unsigned long *)0xF0020008 // Control and status register
#define HwHcInterruptStatus *(volatile unsigned long *)0xF002000C // Control and status register
#define HwHcInterruptEnable *(volatile unsigned long *)0xF0020010 // Control and status register
#define HwHcInterruptDisable *(volatile unsigned long *)0xF0020014 // Control and status register
#define HwHcHCCA *(volatile unsigned long *)0xF0020018 // Memory pointer register
#define HwHcPeroidCurrentED *(volatile unsigned long *)0xF002001C // Memory pointer register
#define HwHcControlHeadED *(volatile unsigned long *)0xF0020020 // Memory pointer register
#define HwHcControlCurrentED *(volatile unsigned long *)0xF0020024 // Memory pointer register
#define HwHcBulkHeadED *(volatile unsigned long *)0xF0020028 // Memory pointer register
#define HwHcBulkCurrentED *(volatile unsigned long *)0xF002002C // Memory pointer register
#define HwHcDoneHead *(volatile unsigned long *)0xF0020030 // Memory pointer register
#define HwHcRmInterval *(volatile unsigned long *)0xF0020034 // Frame counter register
#define HwHcFmRemaining *(volatile unsigned long *)0xF0020038 // Frame counter register
#define HwHcFmNumber *(volatile unsigned long *)0xF002003C // Frame counter register
#define HwHcPeriodStart *(volatile unsigned long *)0xF0020040 // Frame counter register
#define HwHcLSThreshold *(volatile unsigned long *)0xF0020044 // Frame counter register
#define HwRhDescriptorA *(volatile unsigned long *)0xF0020048 // Root hub register
#define HwRhDescriptorB *(volatile unsigned long *)0xF002004C // Root hub register
#define HwRhStatus *(volatile unsigned long *)0xF0020050 // Root hub register
#define HwRhPortStatus1 *(volatile unsigned long *)0xF0020054 // Root hub register
#define HwRhPortStatus2 *(volatile unsigned long *)0xF0020058 // Root hub register
#define HwUHINT_ST HwHcInterruptStatus
#define HwUHINT_EN HwHcInterruptEnable
#define HwUHINT_DIS HwHcInterruptDisable
#define HwUH_RHP0 HwRhPortStatus1
#define HwUHCMD_ST HwHcCommandStatus
/************************************************************************
* IDE Interface Register Define (Base Addr = 0xF0030000)
************************************************************************/
#define HwIDE_BASE *(volatile unsigned long *)0xF0030000 // IDE Base Register
#define HwCS0n *(volatile unsigned long *)0xF0030000 // R/W, PIO CS0n Access register
#define HwCS00 0xF0030000 // PIO CS00 Register Address
#define REG_PTR *(volatile unsigned short *) // get the content of pointer
#define IDE_BASE_CS0 0xF0030000
#define HwIDE_RD_DATA (REG_PTR(IDE_BASE_CS0+(0x00<<2)+ 0x00))
#define HwIDE_WR_DATA HwIDE_RD_DATA
#define HwCS1n *(volatile unsigned long *)0xF0030020 // R/W, PIO CS1n Access register
#define HwCS10 ⌨️ 快捷键说明
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