📄 tcc79x_physical.h
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#define HwTVEGLK_XT24_27MHZ HwZERO // 27MHz Clock input
#define HwTVEGLK_GLKEN_RST_EN Hw3 // Reset Genlock
#define HwTVEGLK_GLKEN_RST_DIS ~Hw3 // Release Genlock
#define HwTVEGLK_GLKE(X) ((X)*Hw1)
#define HwTVEGLK_GLKE_INT HwTVEGLK_GLKE(0) // Chroma Fsc is generated from internal constants based on current user setting
#define HwTVEGLK_GLKE_RTCO HwTVEGLK_GLKE(2) // Chroma Fsc is adjusted based on external RTCO input
#define HwTVEGLK_GLKE_CLKI HwTVEGLK_GLKE(3) // Chroma Fsc tracks non standard encoder clock (CLKI) frequency
#define HwTVEGLK_GLKE_MASK HwTVEGLK_GLKE(3) //
#define HwTVEGLK_GLKEN_GLKPL_HIGH Hw0 // PAL ID polarity is active high
#define HwTVEGLK_GLKEN_GLKPL_LOW HwZERO // PAL ID polarity is active low
#define HwTVESCH *(volatile unsigned long *)0xF9000010 // R/W, Color burst phase relation control (relative to Sync trip)
#define HwTVEHUE *(volatile unsigned long *)0xF9000014 // R/W, Active video Color burst phase relation control (relative to color burst)
#define HwTVESAT *(volatile unsigned long *)0xF9000018 // R/W, Active video Chroma gain control relative to color burst gain
#define HwTVECONT *(volatile unsigned long *)0xF900001C // R/W, Luma gain control
#define HwTVEBRIGHT *(volatile unsigned long *)0xF9000020 // R/W, Luma offset control
#define HwTVEFSC_ADJM *(volatile unsigned long *)0xF9000024 // R/W, MSB of Fsc adjust value
#define HwTVEFSC_ADJL *(volatile unsigned long *)0xF9000028 // R/W, LSB of Fsc adjust value
#define HwTVECMDC *(volatile unsigned long *)0xF900002C // R/W, Encoder Mode Control Register C
#define HwTVECMDC_CSMDE_EN Hw7 // Composite Sync mode enabled
#define HwTVECMDC_CSMDE_DIS ~Hw7 // Composite Sync mode disabled (pin is tri-stated)
#define HwTVECMDC_CSMD(X) ((X)*Hw5)
#define HwTVECMDC_CSMD_CSYNC HwTVECMDC_CSMD(0) // CSYN pin is Composite sync signal
#define HwTVECMDC_CSMD_KEYCLAMP HwTVECMDC_CSMD(1) // CSYN pin is Keyed clamp signal
#define HwTVECMDC_CSMD_KEYPULSE HwTVECMDC_CSMD(2) // CSYN pin is Keyed pulse signal
#define HwTVECMDC_CSMD_MASK HwTVECMDC_CSMD(3)
#define HwTVECMDC_RGBSYNC(X) ((X)*Hw3)
#define HwTVECMDC_RGBSYNC_NOSYNC HwTVECMDC_RGBSYNC(0) // Disable RGBSYNC (when output is configured for analog EGB mode)
#define HwTVECMDC_RGBSYNC_RGB HwTVECMDC_RGBSYNC(1) // Sync on RGB output signal (when output is configured for analog EGB mode)
#define HwTVECMDC_RGBSYNC_G HwTVECMDC_RGBSYNC(2) // Sync on G output signal (when output is configured for analog EGB mode)
#define HwTVECMDC_RGBSYNC_MASK HwTVECMDC_RGBSYNC(3)
#define HwTVEDACSEL *(volatile unsigned long *)0xF9000040 // R/W, DAC Output Selection
#define HwTVEDACSEL_DACSEL_CODE0 HwZERO // Data output is diabled (output is code '0')
#define HwTVEDACSEL_DACSEL_CVBS Hw0 // Data output in CVBS format
#define HwTVEDACPD *(volatile unsigned long *)0xF9000050 // R/W, DAC Power Down
#define HwTVEDACPD_PD_EN Hw0 // DAC Power Down Enabled
#define HwTVEDACPD_PD_DIS ~Hw0 // DAC Power Down Disabled
#define HwTVEICNTL *(volatile unsigned long *)0xF9000080 // R/W, Sync Control
#define HwTVEICNTL_FSIP_ODDHIGH Hw7 // Odd field active high
#define HwTVEICNTL_FSIP_ODDLOW HwZERO // Odd field active low
#define HwTVEICNTL_VSIP_HIGH Hw6 // V-sync active high
#define HwTVEICNTL_VSIP_LOW HwZERO // V-sync active low
#define HwTVEICNTL_HSIP_HIGH Hw5 // H-sync active high
#define HwTVEICNTL_HSIP_LOW HwZERO // H-sync active low
#define HwTVEICNTL_HSVSP_RISING Hw4 // H/V-sync latch enabled at rising edge
#define HwTVEICNTL_HVVSP_FALLING HwZERO // H/V-sync latch enabled at falling edge
#define HwTVEICNTL_VSMD_START Hw3 // Even/Odd field H/V sync output are aligned to video line start
#define HwTVEICNTL_VSMD_MID HwZERO // Even field H/V sync output are aligned to video line midpoint
#define HwTVEICNTL_ISYNC(X) ((X)*Hw0)
#define HwTVEICNTL_ISYNC_FSI HwTVEICNTL_ISYNC(0) // Alignment input format from FSI pin
#define HwTVEICNTL_ISYNC_HVFSI HwTVEICNTL_ISYNC(1) // Alignment input format from HSI,VSI,FSI pin
#define HwTVEICNTL_ISYNC_HVSI HwTVEICNTL_ISYNC(2) // Alignment input format from HSI,VSI pin
#define HwTVEICNTL_ISYNC_VFSI HwTVEICNTL_ISYNC(3) // Alignment input format from VSI,FSI pin
#define HwTVEICNTL_ISYNC_VSI HwTVEICNTL_ISYNC(4) // Alignment input format from VSI pin
#define HwTVEICNTL_ISYNC_ESAV_L HwTVEICNTL_ISYNC(5) // Alignment input format from EAV,SAV codes (line by line)
#define HwTVEICNTL_ISYNC_ESAV_F HwTVEICNTL_ISYNC(6) // Alignment input format from EAV,SAV codes (frame by frame)
#define HwTVEICNTL_ISYNC_FREE HwTVEICNTL_ISYNC(7) // Alignment is free running (Master mode)
#define HwTVEICNTL_ISYNC_MASK HwTVEICNTL_ISYNC(7)
#define HwTVEHVOFFST *(volatile unsigned long *)0xF9000084 // R/W, Offset Control
#define HwTVEHVOFFST_INSEL(X) ((X)*Hw6)
#define HwTVEHVOFFST_INSEL_BW16_27MHZ HwTVEHVOFFST_INSEL(0) // 16bit YUV 4:2:2 sampled at 27MHz
#define HwTVEHVOFFST_INSEL_BW16_13P5MHZ HwTVEHVOFFST_INSEL(1) // 16bit YUV 4:2:2 sampled at 13.5MHz
#define HwTVEHVOFFST_INSEL_BW8_13P5MHZ HwTVEHVOFFST_INSEL(2) // 8bit YUV 4:2:2 sampled at 13.5MHz
#define HwTVEHVOFFST_INSEL_MASK HwTVEHVOFFST_INSEL(3)
#define HwTVEHVOFFST_VOFFST_256 Hw3 // Vertical offset bit 8 (Refer to HwTVEVOFFST)
#define HwTVEHVOFFST_HOFFST_1024 Hw2 // Horizontal offset bit 10 (Refer to HwTVEHOFFST)
#define HwTVEHVOFFST_HOFFST_512 Hw1 // Horizontal offset bit 9 (Refer to HwTVEHOFFST)
#define HwTVEHVOFFST_HOFFST_256 Hw0 // Horizontal offset bit 8 (Refer to HwTVEHOFFST)
#define HwTVEVOFFST *(volatile unsigned long *)0xF9000088 // R/W, Vertical Offset Control (bit [7:0], bit 8 is at HwTVEHVOFFST)
#define HwTVEHOFFST *(volatile unsigned long *)0xF900008C // R/W, Horizontal Offset Control (bit [7:0], bit 10~8 is at HwTVEHVOFFST)
#define HwTVEHSVSO *(volatile unsigned long *)0xF9000090 // R/W, Sync Output Control
#define HwTVEHSVSO_VSOB_256 Hw6 // VSOB bit 8 (Refer to HwVSOB)
#define HwTVEHSVSO_HSOB_1024 Hw5 // HSOB bit 10 (Refer to HwHSOB)
#define HwTVEHSVSO_HSOB_512 Hw4 // HSOB bit 9 (Refer to HwHSOB)
#define HwTVEHSVSO_HSOB_256 Hw3 // HSOB bit 8 (Refer to HwHSOB)
#define HwTVEHSVSO_HSOE_1024 Hw2 // HSOE bit 10 (Refer to HwHSOE)
#define HwTVEHSVSO_HSOE_512 Hw1 // HSOE bit 9 (Refer to HwHSOE)
#define HwTVEHSVSO_HSOE_256 Hw0 // HSOE bit 8 (Refer to HwHSOE)
#define HwTVEHSOE *(volatile unsigned long *)0xF9000094 // R/W, Trailing Edge of Horizontal Sync Control (bit[7:0], bit 10~8 is at HwTVEHSVSO)
#define HwTVEHSOB *(volatile unsigned long *)0xF9000098 // R/W, Leading Edge of Horizontal Sync Control (bit[7:0], bit 10~8 is at HwTVEHSVSO)
#define HwTVEVSOB *(volatile unsigned long *)0xF900009C // R/W, Leading Edge of Vertical Sync Control (bit[7:0], bit 8 is at HwTVEHSVSO)
#define HwTVEVSOE *(volatile unsigned long *)0xF90000A0 // R/W, Trailing Edge of Vertical Sync Control
#define HwTVEVSOE_VSOST(X) ((X)*Hw6) // Programs V-sync relative location for Odd/Even Fields.
#define HwTVEVSOE_NOVRST_EN Hw5 // No vertical reset on every field
#define HwTVEVSOE_NOVRST_NORMAL HwZERO // Normal vertical reset operation (interlaced output timing)
#define HwTVEVSOE_VSOE(X) ((X)*Hw0) // Trailing Edge of Vertical Sync Control
#define HwTVEVENCON *(volatile unsigned long *)0xF9000800 // R/W, Connection between LCDC & TVEncoder Control
#define HwTVEVENCON_EN_EN Hw0 // Connection between LCDC & TVEncoder Enabled
#define HwTVEVENCON_EN_DIS ~Hw0 // Connection between LCDC & TVEncoder Disabled
#define HwTVEVENCIF *(volatile unsigned long *)0xF9000804 // R/W, I/F between LCDC & TVEncoder Selection
// #define HwTVEVENCIF_DAC_EN Hw2 // Enable DAC of TVEncoder
// #define HwTVEVENCIF_MV_1 Hw1 // reserved
#define HwTVEVENCIF_FMT_1 Hw0 // PXDATA[7:0] => CIN[7:0], PXDATA[15:8] => YIN[7:0]
#define HwTVEVENCIF_FMT_0 HwZERO // PXDATA[7:0] => YIN[7:0], PXDATA[15:8] => CIN[7:0]
/***********************************************************************
* USB Controller Register Define (Base Addr = 0xF0010000)
************************************************************************/
#define HwUSBD_BASE *(volatile unsigned long *)0xF0010000 // USB Device Base Register
#define HwIR *(volatile unsigned long *)0xF0010000 // R/W, Index Register
#define HwEIR *(volatile unsigned long *)0xF0010004 // R/W, Endpoint Interrupt Register
#define HwEIR_EP0INT Hw0 // W : Clear the EP0 interrupt flag, R : Indicates that the USB EP0 interrupt has been generated
#define HwEIR_EP1INT Hw1 // W : Clear the EP1 interrupt flag, R : Indicates that the USB EP1 interrupt has been generated
#define HwEIR_EP2INT Hw2 // W : Clear the EP2 interrupt flag, R : Indicates that the USB EP2 interrupt has been generated
#define HwEIR_EP3INT Hw3 // W : Clear the EP3 interrupt flag, R : Indicates that the USB EP3 interrupt has been generated
#define HwEIER *(volatile unsigned long *)0xF0010008 // R/W, Endpoint Interrupt Enable Register
#define HwEIER_EP0INT_EN Hw0 // Enable EP0 interrupt
#define HwEIER_EP0INT_DIS ~Hw0 // Disable EP0 interrupt
#define HwEIER_EP1INT_EN Hw1 // Enable EP1 interrupt
#define HwEIER_EP1INT_DIS ~Hw1 // Disable EP1 interrupt
#define HwEIER_EP2INT_EN Hw2 // Enable EP2 interrupt
#define HwEIER_EP2INT_DIS ~Hw2 // Disable EP2 interrupt
#define HwEIER_EP3INT_EN Hw3 // Enable EP3 interrupt
#define HwEIER_EP3INT_DIS ~Hw3 // Disable EP3 interrupt
#define HwFAR *(volatile unsigned long *)0xF001000C // Function Address Register
#define HwFNR *(volatile unsigned long *)0xF0010010 // Frame Number Register
#define HwFNR_FTL Hw14 // Frame Timer Lock
#define HwFNR_SM Hw13 // SOF Missing
#define HwFNR_FN_MASK 0x7FF // Frame Number Mask
#define HwEDR *(volatile unsigned long *)0xF0010014 // R/W, Endpoint Direction Register
#define HwEDR_EP0_TX Hw0 // Tx Endpoint
#define HwEDR_EP0_RX ~Hw0 // Rx Endpoint
#define HwEDR_EP1_TX Hw1 // Tx Endpoint
#define HwEDR_EP1_RX ~Hw1 // Rx Endpoint
#define HwEDR_EP2_TX Hw2 // Tx Endpoint
#define HwEDR_EP2_RX ~Hw2 // Rx Endpoint
#define HwEDR_EP3_TX Hw3 // Tx Endpoint
#define HwEDR_EP3_RX ~Hw3 // Rx Endpoint
#define HwUTST *(volatile unsigned long *)0xF0010018 // Test Register
#define HwUTST_VBUS_ON Hw15 //
#define HwUTST_VBUS_OFF ~Hw15 //
#define HwUTST_EUERR Hw13 // EB underrun error in transceiver
#define HwUTST_PERR Hw12 // PID Error Flag
#define HwUTST_TPS_ON Hw3 // Transmit test packets
#define HwUTST_TPS_OFF ~Hw3 // Stop Transmitting
#define HwUTST_TKS_ON Hw2 // Transmit test K packets
#define HwUTST_TKS_OFF ~Hw2 // Stop Transmitting
#define HwUTST_TJS_ON Hw1 // Transmit test J packets
#define HwUTST_TJS_OFF ~Hw1 // Stop Transmitting
#define HwUTST_TSNS_ON Hw0 // Transmit test SE0 NAK
#define HwUTST_TSNS_OFF ~Hw0 // Stop Transmitting
#define HwSSR *(volatile unsigned long *)0xF001001C // R/W, System Status Register
#define HwSSR_BAERR Hw15 // Byte-Align Error
#define HwSSR_TMERR Hw14 // Timeout Error
#define HwSSR_BSERR Hw13 // Bit Stuff Error
#define HwSSR_TCERR Hw12 // Token CRC Error
#define HwSSR_DCERR Hw11 // Data CRC Error
#define HwSSR_EOERR Hw10 // EB Overrun Error
#define HwSSR_VBUS_OFF Hw9 // VBUS is in Off state.(active when VBUS OFF interrupt is enabled)
#define HwSSR_VBUS_ON Hw8 // VBUS is in ON state.(active when VBUS ON interrupt is enabled)
#define HwSSR_TBM Hw7 // Toggle Bit Mismatch Error
#define HwSSR_DP_HIGH Hw6 // D+ == High State
#define HwSSR_DP_LOW ~Hw6 // D+ == Low State
#define HwSSR_DN_HIGH Hw5 // D- == High State
#define HwSSR_DN_LOW ~Hw5 // D- == Low State
#define HwSSR_HSP_HIGH Hw4 // Host is High Speed.
#define HwSSR_HSP_FULL ~Hw4 // Host is Full Speed.
#define HwSSR_SDE_END Hw3 // Speed Detection is Ended.
#define HwSSR_HFRM Hw2 // Host sends Resume signaling.
#define HwSSR_HFSUSP Hw1 // Host sends Suspend signaling.
#define HwSSR_HFRES Hw0 // Host sends Reset signaling.
#define HwSCR *(volatile unsigned long *)0xF0010020 // R/W, System Control Register
#define HwSCR_DTZIEN_EN Hw14 // DMA Total Count Zero Interrupt Enabled
#define HwSCR_DTZIEN_DIS ~Hw14 // DMA Total Count Zero Interrupt Disabled
#define HwSCR_DIEN_EN Hw12 // Dual Interrupt Enabled
#define HwSCR_DIEN_DIS ~Hw12 // Dual Interrupt Disabled
#define HwSCR_VBUSOFF_EN Hw11 // HwSSR(VBUS OFF flag) Enabled
#define HwSCR_VBUSOFF_DIS ~Hw11 // HwSSR(VBUS OFF flag) Disabled
#define HwSCR_VBUSON_EN Hw10 // HwSSR(VBUS ON flag) Enabled
#define HwSCR_VBUSON_DIS ~Hw10 // HwSSR(VBUS ON flag) Disabled
#define HwSCR_RWDE_EN Hw9 // High byte data [15:8] is sent first.
#define HwSCR_RWDE_DIS ~Hw9 // Low byte data [7:0] is sent first.
#define HwSCR_EIE_EN Hw8 // Error Interrupt Enable
#define HwSCR_EIE_DIS ~Hw8 // Error Interrupt Disable
#define HwSCR_SDE_EN Hw6 // Speed Detection End Interrupt Enable
#define HwSCR_SDE_DIS ~Hw6 // Speed Detection End Interrupt Disable
#define HwSCR_RRDE_EN Hw5 // First received data is loaded in Low byte [7:0]
#define HwSCR_RRDE_DIS ~Hw5 // First received data is loaded in High byte [15:8]
#define HwSCR_IPS_HIGH Hw4 // Active High Interrupt Polarity
#define HwSCR_IPS_LOW ~Hw4 // Active Low Interrupt Polarity
#define HwSCR_MFRM_ON Hw2 // USB Core generates Resume signaling.
#define HwSCR_MFRM_OFF ~Hw2 // USB Core stop generating Resume signaling.
#define HwSCR_HSUSPE_EN Hw1 // USB Core can repond to the Suspend signaling from HOST.
#define HwSCR_HSUSPE_DIS ~Hw1 // USB Core cannot repond to the Suspend signaling from HOST.
#define HwSCR_HRESE_EN Hw0 // USB Core can repond to the Reset signaling from HOST.
#define HwSCR_HRESE_DIS ~Hw0 // USB Core cannot repond to the Reset signaling from HOST.
#define HwEP0SR *(volatile unsigned long *)0xF0010024 // R/W, EP0 Status Register
#define HwEP0SR_LWO Hw6 // Last Word Odd
#define HwEP0SR_SHT Hw4 // Stall Handshake Transmitted
#define HwEP0SR_TST Hw1 // TX Successfully Transmitted
#define HwEP0SR_RSR Hw0 // RX Successfully Received
#define HwEP0CR *(volatile unsigned long *)0xF0010028 // R/W, EP0 Control Register
#define HwEP0CR_TTE_EN Hw3 // TX Test Enable
#define HwEP0CR_TTE_DIS ~Hw3 // TX Test Disable
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