📄 tcc79x_physical.h
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#define HwY2RP1 *(volatile unsigned long *)0xF00000E8 // W, YCbCr to RGB Conversion Parameter 1
#define HwLPMCTRL *(volatile unsigned long *)0xF00000F0 // W, PIP Mode Control
#define HwLPMCTRL_PL_INT Hw7 // PIP in TCCxxx Chip
#define HwLPMCTRL_PL_EXT HwZERO // PIP in External Chip
#define HwLPMCTRL_PS_WINDOW Hw6 // PIP with Windowing Method
#define HwLPMCTRL_PS_CHROMA HwZERO // PIP with Chroma-key Method
#define HwLPMCTRL_FL_FLUSH Hw5 // FIFO Flush
#define HwLPMCTRL_DS_DE Hw4 // Detect using Data Enable or H-Sync
#define HwLPMCTRL_DS_VS HwZERO // Detect using V-Sync
#define HwLPMCTRL_DEP_LOW Hw3 // Data Enable Polarity : Active Low
#define HwLPMCTRL_DEP_HIGH HwZERO // Data Enable Polarity : Active High
#define HwLPMCTRL_VP_LOW Hw2 // V-Sync Polarity : Active Low
#define HwLPMCTRL_VP_HIGH HwZERO // V-Sync Polarity : Active High
#define HwLPMCTRL_ENS_HS Hw1 // Use H-Sync
#define HwLPMCTRL_ENS_DE HwZERO // Use ACBias (DATAEN)
#define HwLPMCTRL_EN_EN Hw0 // Enable PIP
#define HwLPMW0 *(volatile unsigned long *)0xF00000F4 // W, PIP Mode Windowing 0
#define HwLPMW1 *(volatile unsigned long *)0xF00000F8 // W, PIP Mode Windowing 1
#define HwLPMH *(volatile unsigned long *)0xF00000FC // W, PIP Mode Height
#define HwLPMC *(volatile unsigned long *)0xF0000100 // W, PIP Mode Chroma-Key
#define HwLPMMC *(volatile unsigned long *)0xF0000104 // W, PIP Mode Mask Chroma-Key
#define HwLCDLUT *(volatile unsigned long *)0xF0000C00 // W, LCD Lookup Table
typedef volatile struct {
unsigned LCTRL;
unsigned LBC;
unsigned LCLKDIV;
unsigned LHTIME1;
unsigned LHTIME2;
unsigned LVTIME1;
unsigned LVTIME2;
unsigned LVTIME3;
unsigned LVTIME4;
unsigned LLUTR;
unsigned LLUTG;
unsigned LLUTB;
unsigned LDP7L;
unsigned LDP7H;
unsigned LDP5;
unsigned LDP4;
unsigned LDP3;
unsigned LCP1;
unsigned LCP2;
unsigned LK1;
unsigned LK2;
unsigned LKM1;
unsigned LKM2;
unsigned LDS;
unsigned LSTATUS;
unsigned LIM;
unsigned LI0C;
unsigned LI0P;
unsigned LI0S;
unsigned LI0BA0;
unsigned LI0CA;
unsigned LI0BA1;
unsigned LI0BA2;
unsigned LI0O;
unsigned LI0SR;
unsigned LI1C;
unsigned LI1P;
unsigned LI1S;
unsigned LI1BA0;
unsigned LI1CA;
unsigned LI1BA1;
unsigned LI1BA2;
unsigned LI1O;
unsigned LI1SR;
unsigned LI2C;
unsigned LI2P;
unsigned LI2S;
unsigned LI2BA0;
unsigned LI2CA;
unsigned LI2BA1;
unsigned LI2BA2;
unsigned LI2O;
unsigned LI2SR;
} sHwLCD;
/************************************************************************
* LCD System Interface Register Define (Base Addr = 0xF0000400)
************************************************************************/
#define HwLCDSI_BASE *(volatile unsigned long *)0xF0000400 // LCDSI Base Register
#define HwLCDSICTRL0 *(volatile unsigned long *)0xF0000400 // R/W, Control Register for LCDSI
#define HwLCDSICTRL0_IA_LOW Hw15 // LACBIAS(Data Enable) signal is active low
#define HwLCDSICTRL0_IVS_LOW Hw14 // LYSYNC signal is active low
#define HwLCDSICTRL0_CS_1 Hw7 // If IM is high, CS1 is active during operationgs. Otherwise, it is no applicable. These bits are only available when IM is high
#define HwLCDSICTRL0_RSP_HIGH Hw6 // If IM is high, RS is high. Otherwise, it is not applicable
#define HwLCDSICTRL0_FMT_8RGB565 HwZERO // LCDC pixel data output:RGB565
// LCDSI pixel data output(8bits):RGB565[7:0], RGB565[15:8]
// LCDSI CTRL1-4.WBW must be 1
#define HwLCDSICTRL0_FMT_16RGB565 (Hw4+Hw3) // LCDC pixel data output:RGB565
// LCDSI pixel data output(16bits):RGB565[15:0]
// LCDSI CTRL1-4.WBW must be 0
#define HwLCDSICTRL0_FMT_8RGB888 Hw2 // LCDC pixel data output:RGB888
// LCDSI pixel data output(8bits):R[7:0],G[7:0],B[7:0]
// LCDSI CTRL1-4.WBW must be 1
#define HwLCDSICTRL0_FMT_9RGB888 (Hw3+Hw2) // LCDC pixel data output:RGB888
// LCDSI pixel data output(9bits):{G[2:0],R[5:0]},{B[5:0],G[5:3]}
// LCDSI CTRL1-4.WBW must be 0
#define HwLCDSICTRL0_FMT_16RGB888 (Hw4+Hw2) // LCDC pixel data output:RGB888
// LCDSI pixel data output(16bits):RGB565[15:0]
// LCDSI CTRL1-4.WBW must be 0
#define HwLCDSICTRL0_FMT_18RGB888 (Hw4+Hw3+Hw2) // LCDC pixel data output:RGB888
// LCDSI pixel data output(16bits):{B[3:0],G[5:0],R[5:0]},B[5:4]
// LCDSI CTRL1-4.WBW must be 0
#define HwLCDSICTRL0_OM Hw1 //
#define HwLCDSICTRL0_IM Hw0 //
#define HwLCDSICTRL1 *(volatile unsigned long *)0xF0000800 // R/W, Control Register for nCS0 when RS = 0
#define HwLCDSICTRL1_BW_8 HwZERO // Data width is 8 bits
#define HwLCDSICTRL1_BW_16 Hw15 // Data width is 16 bits
#define HwLCDSICTRL1_BW_18 (Hw31+Hw15) // Data width is 18 bits
#define HwLCDSICTRL_BW_8 HwZERO // Data width is 8 bits
#define HwLCDSICTRL_BW_16 Hw15 // Data width is 16 bits
#define HwLCDSICTRL_BW_18 (Hw31+Hw15) // Data width is 18 bits
#define HwLCDSICTRL2 *(volatile unsigned long *)0xF0000804 // R/W, Control Register for nCS0 when RS = 1
#define HwLCDSICTRL2_BW_8 HwZERO // Data width is 8 bits
#define HwLCDSICTRL2_BW_16 Hw15 // Data width is 16 bits
#define HwLCDSICTRL2_BW_18 (Hw31+Hw15) // Data width is 18 bits
#define HwLCDSICTRL3 *(volatile unsigned long *)0xF0000808 // R/W, Control Register for nCS1 when RS = 0
#define HwLCDSICTRL3_BW_8 HwZERO // Data width is 8 bits
#define HwLCDSICTRL3_BW_16 Hw15 // Data width is 16 bits
#define HwLCDSICTRL3_BW_18 (Hw31+Hw15) // Data width is 18 bits
#define HwLCDSICTRL4 *(volatile unsigned long *)0xF000080C // R/W, Control Register for nCS0 when RS = 1
#define HwLCDSICTRL4_BW_8 HwZERO // Data width is 8 bits
#define HwLCDSICTRL4_BW_16 Hw15 // Data width is 16 bits
#define HwLCDSICTRL4_BW_18 (Hw31+Hw15) // Data width is 18 bits
#define HwLCDSICS0RS0 *(volatile short *)0xF0000810 // R/W, If this register is read or written, reading or writing operations are generated on nCS0 while RS = 0
#define HwLCDSICS0RS1 *(volatile short *)0xF0000818 // R/W, If this register is read or written, reading or writing operations are generated on nCS0 while RS = 1
#define HwLCDSICS1RS0 *(volatile short *)0xF0000820 // R/W, If this register is read or written, reading or writing operations are generated on nCS1 while RS = 0
#define HwLCDSICS1RS1 *(volatile short *)0xF0000828 // R/W, If this register is read or written, reading or writing operations are generated on nCS1 while RS = 1
#define HwLCDSICTRL5 *(volatile unsigned long *)0xF0000830 // R/W,
#define HwLCDSICTRL5_WBW Hw31 //
#define HwLCDSICTRL_WBW Hw31 //
#define HwLCDSICTRL6 *(volatile unsigned long *)0xF0000834 // R/W,
#define HwLCDSICTRL6_WBW Hw31 //
#define HwLCDSICTRL7 *(volatile unsigned long *)0xF0000838 // R/W,
#define HwLCDSICTRL7_WBW Hw31 //
#define HwLCDSICTRL8 *(volatile unsigned long *)0xF000083C // R/W,
#define HwLCDSICTRL8_WBW Hw31 //
typedef volatile struct {
unsigned CTRL0;
unsigned _Dummy[(0x400-0x4)/4];
unsigned CTRL1;
unsigned CTRL2;
unsigned CTRL3;
unsigned CTRL4;
unsigned CS0RS0;
unsigned _Dummy_1;
unsigned CS0RS1;
unsigned _Dummy_2;
unsigned CS1RS0;
unsigned _Dummy_3;
unsigned CS1RS1;
unsigned _Dummy_4;
unsigned CTRL5;
unsigned CTRL6;
unsigned CTRL7;
unsigned CTRL8;
} sHwLCDSI;
/************************************************************************
* TV Encoder Register Define (Base Addr = 0xF9000000)
************************************************************************/
#define HwTVE_BASE *(volatile unsigned long *)0xF9000000 // TV Encoder Base Register
#define HwTVESTATA *(volatile unsigned long *)0xF9000000 // R, Status Register
#define HwTVECMDA *(volatile unsigned long *)0xF9000004 // R/W, Encoder Mode Control Register A
#define HwTVECMDA_PWDENC_PD Hw7 // Power down mode for entire digital logic of TV encoder
#define HwTVECMDA_FDRST_1 Hw6 // Chroma is free running as compared to H-sync
#define HwTVECMDA_FDRST_0 HwZERO // Relationship between color burst & H-sync is maintained for video standards
#define HwTVECMDA_FSCSEL(X) ((X)*Hw4)
#define HwTVECMDA_FSCSEL_NTSC HwTVECMDA_FSCSEL(0) // Color subcarrier frequency is 3.57954545 MHz for NTSC
#define HwTVECMDA_FSCSEL_PALX HwTVECMDA_FSCSEL(1) // Color subcarrier frequency is 4.43361875 MHz for PAL-B,D,G,H,I,N
#define HwTVECMDA_FSCSEL_PALM HwTVECMDA_FSCSEL(2) // Color subcarrier frequency is 3.57561149 MHz for PAL-M
#define HwTVECMDA_FSCSEL_PALCN HwTVECMDA_FSCSEL(3) // Color subcarrier frequency is 3.58205625 MHz for PAL-combination N
#define HwTVECMDA_FSCSEL_MASK HwTVECMDA_FSCSEL(3)
#define HwTVECMDA_PEDESTAL Hw3 // Video Output has a pedestal
#define HwTVECMDA_NO_PEDESTAL HwZERO // Video Output has no pedestal
#define HwTVECMDA_PIXEL_SQUARE Hw2 // Input data is at square pixel rates.
#define HwTVECMDA_PIXEL_601 HwZERO // Input data is at 601 rates.
#define HwTVECMDA_IFMT_625 Hw1 // Output data has 625 lines
#define HwTVECMDA_IFMT_525 HwZERO // Output data has 525 lines
#define HwTVECMDA_PHALT_PAL Hw0 // PAL encoded chroma signal output
#define HwTVECMDA_PHALT_NTSC HwZERO // NTSC encoded chroma signal output
#define HwTVECMDB *(volatile unsigned long *)0xF9000008 // R/W, Encoder Mode Control Register B
#define HwTVECMDB_YBIBLK_BLACK Hw4 // Video data is forced to Black level for Vertical non VBI processed lines.
#define HwTVECMDB_YBIBLK_BYPASS HwZERO // Input data is passed through forn non VBI processed lines.
#define HwTVECMDB_CBW(X) ((X)*Hw2)
#define HwTVECMDB_CBW_LOW HwTVECMDB_CBW(0) // Low Chroma band-width
#define HwTVECMDB_CBW_MEDIUM HwTVECMDB_CBW(1) // Medium Chroma band-width
#define HwTVECMDB_CBW_HIGH HwTVECMDB_CBW(2) // High Chroma band-width
#define HwTVECMDB_CBW_MASK HwTVECMDB_CBW(3) //
#define HwTVECMDB_YBW(X) ((X)*Hw0)
#define HwTVECMDB_YBW_LOW HwTVECMDB_YBW(0) // Low Luma band-width
#define HwTVECMDB_YBW_MEDIUM HwTVECMDB_YBW(1) // Medium Luma band-width
#define HwTVECMDB_YBW_HIGH HwTVECMDB_YBW(2) // High Luma band-width
#define HwTVECMDB_YBW_MASK HwTVECMDB_YBW(3) //
#define HwTVEGLK *(volatile unsigned long *)0xF900000C // R/W, Encoder Clock Generator Register
#define HwTVEGLK_XT24_24MHZ Hw4 // 24MHz Clock input
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