tcc79x_physical.h

自己在wince的环境下做的一移动数字电视驱动

/****************************************************************************
 *   FileName    : TCC79x.h
 *   Description : TCC79x REGISTER DEFINE FUNCTION
 ****************************************************************************
 *
 *   TCC Version 1.0
 *   Copyright (c) Telechips, Inc.
 *   ALL RIGHTS RESERVED
 *
 *  HISTORY OF MODIFIED
 *	2006 MAR. 15 Created BY JY.JANG
 *
 ****************************************************************************/

/****************************************************************************

  Revision History

 ****************************************************************************

 ****************************************************************************/

/************************************************************************
*	TCC79x Internal Register Definition File
************************************************************************/
#ifndef	__TCC79x_H__
#define	__TCC79x_H__

enum {
	IRQ_EI0,
	IRQ_EI1,
	IRQ_EI2,
	IRQ_EI3,
	IRQ_RTC,
	IRQ_GPSB,
	IRQ_TC0,	
	IRQ_TC1,
	IRQ_SCORE,
	IRQ_SPDTX,
	IRQ_SEL0,
	IRQ_SEL1,
	IRQ_SC,
	IRQ_I2C,
	IRQ_DAIRX,
	IRQ_DAITX,
	IRQ_CDRX,
	IRQ_EHI,
	IRQ_UT,
	IRQ_SEL2,
	IRQ_G2D,
	IRQ_UD,
	IRQ_UH,
	IRQ_DMA,
	IRQ_HDD,
	IRQ_SEL3,
	IRQ_NFC,
	IRQ_SD,
	IRQ_CAM,
	IRQ_LCD,
	IRQ_ADC,
	IRQ_SEL4,
	IRQ_MaxNum
};
#define	IRQ_VIDEO		IRQ_SEL0
#define	IRQ_EHI0		IRQ_SEL0
#define	IRQ_EI4			IRQ_SEL0
#define	IRQ_GPSB_SEL1	IRQ_SEL1
#define	IRQ_EHI1_SEL1	IRQ_SEL1
#define	IRQ_EI5			IRQ_SEL1
#define	IRQ_UT_SEL2		IRQ_SEL2
#define	IRQ_EHI1_SEL2	IRQ_SEL2
#define	IRQ_MS			IRQ_SEL3
#define	IRQ_EI6			IRQ_SEL3
#define	IRQ_GPSB_SEL4	IRQ_SEL4
#define	IRQ_ECC			IRQ_SEL4
#define	IRQ_EI7			IRQ_SEL4
#define	IRQ_UDMA		IRQ_SEL4

/************************************************************************
*	Bit Field Definition
************************************************************************/
#define	Hw37									(1LL << 37)
#define	Hw36									(1LL << 36)
#define	Hw35									(1LL << 35)
#define	Hw34									(1LL << 34)
#define	Hw33									(1LL << 33)
#define	Hw32									(1LL << 32)
#define	Hw31									0x80000000
#define	Hw30									0x40000000
#define	Hw29									0x20000000
#define	Hw28									0x10000000
#define	Hw27									0x08000000
#define	Hw26									0x04000000
#define	Hw25									0x02000000
#define	Hw24									0x01000000
#define	Hw23									0x00800000
#define	Hw22									0x00400000
#define	Hw21									0x00200000
#define	Hw20									0x00100000
#define	Hw19									0x00080000
#define	Hw18									0x00040000
#define	Hw17									0x00020000
#define	Hw16									0x00010000
#define	Hw15									0x00008000
#define	Hw14									0x00004000
#define	Hw13									0x00002000
#define	Hw12									0x00001000
#define	Hw11									0x00000800
#define	Hw10									0x00000400
#define	Hw9										0x00000200
#define	Hw8										0x00000100
#define	Hw7										0x00000080
#define	Hw6										0x00000040
#define	Hw5										0x00000020
#define	Hw4										0x00000010
#define	Hw3										0x00000008
#define	Hw2										0x00000004
#define	Hw1										0x00000002
#define	Hw0										0x00000001
#define	HwZERO									0x00000000

#define	HwVERSION								*(volatile unsigned long *)0xE0001FFC

/************************************************************************
*	LCD INTERFACE Register Define				(Base Addr = 0xF0000000)
************************************************************************/
#define	HwLCD_BASE							*(volatile unsigned long *)0xF0000000	// LCD Control Base Register

#define	HwLCTRL									*(volatile unsigned long *)0xF0000000	// W, LCD Control Register
	#define	HwLCTRL_Y2R2_EN							Hw31									// YUV to RGB Channel Converter Enable 2
	#define	HwLCTRL_AEN2_EN							Hw30									// Alpha Blend Enable 2
	#define	HwLCTRL_CEN2_EN							Hw29									// Chroma Key Enable 2
	#define	HwLCTRL_Y2R1_EN							Hw28									// YUV to RGB Channel Converter Enable 1
	#define	HwLCTRL_AEN1_EN							Hw27									// Alpha Blend Enable 1
	#define	HwLCTRL_CEN1_EN							Hw26									// Chroma Key Enable 1
	#define	HwLCTRL_Y2R0_EN							Hw25									// YUV to RGB Channel Converter Enable 0
	#define	HwLCTRL_656_EN							Hw24									// CCIR 601 to 656 Enable
	#define	HwLCTRL_CL_1							Hw23									// Pixel Clock is operated without Buffer Full Signal
	#define	HwLCTRL_CL_0							HwZERO									// Pixel Clock is operated by Buffer Full Signal of LCDSI & PIP mode
	#define	HwLCTRL_BPP(X)							((X)*Hw20)								// Bit Per Pixel
	#define	HwLCTRL_BPP_1							HwZERO									// Bit Per Pixel = 1bbp
	#define	HwLCTRL_BPP_2							Hw20									// Bit Per Pixel = 2bbp 
	#define	HwLCTRL_BPP_4							Hw21									// Bit Per Pixel = 4bbp
	#define	HwLCTRL_BPP_332							(Hw21+Hw20)								// Bit Per Pixel = 332bbp
	#define	HwLCTRL_BPP_444							Hw22									// Bit Per Pixel = 444bbp
	#define	HwLCTRL_BPP_MASK						(Hw22+Hw21+Hw20)						// Bit Per Pixel Mask
	#define	HwLCTRL_PXDW(X)						((X)*Hw16)								// Pixel Data Width
	#define	HwLCTRL_PXDW_4							HwZERO									// Pixel Data Width = 4pxdw
	#define	HwLCTRL_PXDW_8							Hw16									// Pixel Data Width = 8pxdw
	#define	HwLCTRL_PXDW_8S_RGB					Hw17									// Pixel Data Width = 8pxdw (stripe type: R8-G8-B8)
	#define	HwLCTRL_PXDW_565						(Hw17+Hw16)								// Pixel Data Width = 565pxdw
	#define	HwLCTRL_PXDW_555						Hw18									// Pixel Data Width = 555pxdw
	#define	HwLCTRL_PXDW_18							(Hw18+Hw16)								// Pixel Data Width = 18pxdw
	#define	HwLCTRL_PXDW_8UY						(Hw18+Hw17)								// Pixel Data Width = 8pxdw(UY)
	#define	HwLCTRL_PXDW_8VY						(Hw18+Hw17+Hw16)						// Pixel Data Width = 8pxdw(VY)
	#define	HwLCTRL_PXDW_16YU						Hw19									// Pixel Data Width = 16pxdw(YU)
	#define	HwLCTRL_PXDW_16YV						(Hw19+Hw16)								// Pixel Data Width = 16pxdw(YV)
	#define	HwLCTRL_PXDW_888D_EvGRB				HwLCTRL_PXDW(10)						// Pixel Data Width = 888pxdw (Delta type: odd=RGB, even=GRB)
	#define	HwLCTRL_PXDW_888D_EvRGB				HwLCTRL_PXDW(11)						// Pixel Data Width = 888pxdw (Delta type: odd=GRB, even=RGB)
	#define	HwLCTRL_PXDW_888						HwLCTRL_PXDW(12)						// Pixel Data Width = 888pxdw (stripe type: RGB)
	#define	HwLCTRL_PXDW_8S_RGBD					HwLCTRL_PXDW(13)						// Pixel Data Width = 8pxdw (stripe type with dummy: RGBD)
	#define	HwLCTRL_PXDW_MASK						(Hw20-Hw16)								// Pixel Data Width Mask
	#define	HwLCTRL_ID_INVERTED						Hw15									// Inverted ACBIAS
	#define	HwLCTRL_IV_INVERTED						Hw14									// Inverted Vertical Sync
	#define	HwLCTRL_IH_INVERTED						Hw13									// Inverted Horizontal Sync
	#define	HwLCTRL_IP_FEDGE						Hw12									// Data is driven onto the LCD's data pins on the falling edge of pixel clock pin
	#define	HwLCTRL_CLEN							Hw11									// Clipping Enable
	#define	HwLCTRL_R2Y_EN							Hw10									// RGB to YUV Channel Converter Enable
	#define	HwLCTRL_DP_2							Hw9										// One pixel data per 2 PXCLK cycle is output
	#define	HwLCTRL_NI_PMODE						Hw8										// Non-interlace Mode (Progressive Mode)
	#define	HwLCTRL_TV								Hw7										// TV Mode. In this mode, all values of LVTIMEn registers are divided by 2
	#define	HwLCTRL_TFT								Hw6										// TFT-LCD Mode
	#define	HwLCTRL_STN								Hw5										// STN-LCD Mode
	#define	HwLCTRL_MSEL							Hw4										// Master Select
	#define	HwLCTRL_IEN2_EN							Hw3										// Fetch Enable 2
	#define	HwLCTRL_IEN1_EN							Hw2										// Fetch Enable 1
	#define	HwLCTRL_IEN0_EN							Hw1										// Fetch Enable 0
	#define	HwLCTRL_LEN_EN							Hw0										// LCD Controller Enable

#define	HwLBC									*(volatile unsigned long *)0xF0000004	// W, LCD Background Color Register
	#define	HwLBC_BG2(X)							((X)*Hw16)						// Background Color 2 (Y/B)
	#define	HwLBC_BG2_MASK							(Hw24-Hw16)
	#define	HwLBC_BG1(X)							((X)*Hw8)						// Background Color 1 (Cb/G)
	#define	HwLBC_BG1_MASK							(Hw16-Hw8)
	#define	HwLBC_BG0(X)							((X)*Hw0)						// Background Color 0 (Cr/R)
	#define	HwLBC_BG0_MASK							(Hw8-Hw0)

#define	HwLCLKDIV								*(volatile unsigned long *)0xF0000008	// W, LCD Clock Divider Register
	#define	HwLCLKDIV_CS							Hw31									// Clock source
	#define	HwLCLKDIV_ACDIV(X)						((X)*Hw16)						// AC Bias Divider (STN only)
	#define	HwLCLKDIV_ACDIV_MASK					(Hw24-Hw16)
	#define	HwLCLKDIV_LCLKDIV(X)					((X)*Hw8)						// LCLK clock divider (Used if CS is set to 1)
	#define	HwLCLKDIV_LCLKDIV_MASK					(Hw16-Hw8)
	#define	HwLCLKDIV_PXCLKDIV(X)					((X)*Hw0)						// Pixel clock divider (Pixel clock = Lclk / (2*PXCLKDIV))
	#define	HwLCLKDIV_PXCLKDIV_MASK				(Hw8-Hw0)

#define	HwLHTIME1								*(volatile unsigned long *)0xF000000C	// W, LCD Horizontal Timing Register 1

#define	HwLHTIME2								*(volatile unsigned long *)0xF0000010	// W, LCD Horizontal Timing Register 2
                                        	
#define	HwLVTIME1								*(volatile unsigned long *)0xF0000014	// W, LCD Vertical Timing Register 1
                                        	
#define	HwLVTIME2								*(volatile unsigned long *)0xF0000018	// W, LCD Vertical Timing Register 2
                                        	
#define	HwLVTIME3								*(volatile unsigned long *)0xF000001C	// W, LCD Vertical Timing Register 3
                                        	
#define	HwLVTIME4								*(volatile unsigned long *)0xF0000020	// W, LCD Vertical Timing Register 4
                                        	
#define	HwLLUTR									*(volatile unsigned long *)0xF0000024	// W, LCD Lookup Register for Red
                                        	
#define	HwLLUTG									*(volatile unsigned long *)0xF0000028	// W, LCD Lookup Register for Green
                                        	
#define	HwLLUTB									*(volatile unsigned long *)0xF000002C	// W, LCD Lookup Register for Blue
                                        	
#define	HwLDP7L									*(volatile unsigned long *)0xF0000030	// W, LCD Modulo 7 Dithering Pattern (Low)
                                        	
#define	HwLDP7H									*(volatile unsigned long *)0xF0000034	// W, LCD Modulo 7 Dithering Pattern (High)
                                        	
#define	HwLDP5									*(volatile unsigned long *)0xF0000038	// W, LCD Modulo 5 Dithering Pattern Register
                                        	
#define	HwLDP4									*(volatile unsigned long *)0xF000003C	// W, LCD Modulo 4 Dithering Pattern Register
                                        	
#define	HwLDP3									*(volatile unsigned long *)0xF0000040	// W, LCD 3-bit Dithering Pattern Register