tcc78xwince.h

自己在wince的环境下做的一移动数字电视驱动

typedef struct _REGISTERPRIORITYINTERRUPTCONTROLLER // 0xF3001000
{
	REGISTERBITPRIORITYINTERRUPTCONTROLLER IEN; // Enable Interrupt
	REGISTERBITPRIORITYINTERRUPTCONTROLLER CLR; // Clear Interrupt
	REGISTERBITPRIORITYINTERRUPTCONTROLLER STS; // Interrupt Status
	REGISTERBITPRIORITYINTERRUPTCONTROLLER SEL; // IRQ/FIQ selection
	REGISTERBITPRIORITYINTERRUPTCONTROLLER SRC; // Test interrupt selection
	REGISTERBITPRIORITYINTERRUPTCONTROLLER MSTS; // Masked Interrupt Status
	REGISTERBITPRIORITYINTERRUPTCONTROLLER TIG; // Test interrupt request
	REGISTERBITPRIORITYINTERRUPTCONTROLLER POL; // Polarity of interrupt signal (0 = active high, 1 = active low)
	REGISTERBITPRIORITYINTERRUPTCONTROLLER IRQ; // IRQ interrupt status
	REGISTERBITPRIORITYINTERRUPTCONTROLLER FIQ; // FIQ interrupt status
	REGISTERBITPRIORITYINTERRUPTCONTROLLER MIRQ; // Masked IRQ interrupt status
	REGISTERBITPRIORITYINTERRUPTCONTROLLER MFIQ; // Masked FIQ interrupt status
	REGISTERBITPRIORITYINTERRUPTCONTROLLER MODE; // Trigger mode selection (0 = edge, 1 = level)
	REGISTERBITPRIORITYINTERRUPTCONTROLLER SYNC; // Enable Synchronizing
	REGISTERBITPRIORITYINTERRUPTCONTROLLER WKEN; // Select Wakeup signal
	REGISTERBITPRIORITYINTERRUPTCONTROLLER MODEA; // Edge trigger mode selection (0 = single edge, 1 = both edge)
	REGISTERBITPRIORITYINTERRUPTCONTROLLER INTMSK; // IRQ Output Masking Register
	struct ALLMSK // All Mask Register
	{
		volatile unsigned int IRQ:1; // 0x0 IRQ mask register RW
		volatile unsigned int FIQ:1; // 0x0 FIQ mask register RW
		// 31 ~ 2 - - Undefined -
	};
} REGISTERPRIORITYINTERRUPTCONTROLLER;


typedef struct _REGISTERGPSB // 0xF0057400, 0xF0057800
{
	volatile unsigned int PORT; // 0x00 R/W 0x0000 Data port
	volatile unsigned int STAT; // 0x04 R/W 0x0000 Status register
	volatile unsigned int INTEN; // 0x08 R/W 0x0000 Interrupt enable
	volatile unsigned int MODE; // 0x0C R/W 0x0000 Mode register
	volatile unsigned int CTRL; // 0x10 R/W 0x0000 Control register

	volatile unsigned int UNDEFINED1[3]; // 14, 18, 1c,
	
	volatile unsigned int TXBASE; // 0x20 R/W 0x0000 TX base address register
	volatile unsigned int RXBASE; // 0x24 R/W 0x0000 RX base address register
	volatile unsigned int PACKET; // 0x28 R/W 0x0000 Packet register
	volatile unsigned int DMACTR; // 0x2C R/W 0x0000 DMA control register
	volatile unsigned int DMASTR; // 0x30 R/W 0x0000 DMA status register
} REGISTERGPSB;


typedef struct _REGISTERGPIO // 0xF005A000
{
	volatile unsigned int PORTCFG0; // 0x00 R/W Port Configuration Register 0
	volatile unsigned int PORTCFG1; // 0x04 R/W Port Configuration Register 1
	volatile unsigned int PORTCFG2; // 0x08 R/W Port Configuration Register 2
	volatile unsigned int PORTCFG3; // 0x0C R/W Port Configuration Register 3

	volatile unsigned int UNDEFINED1[4]; // 10, 14, 18, 1c,
	
	volatile unsigned int GPADAT; // 0x20 R/W 0x00000000 GPA Data Register
	volatile unsigned int GPAEN; // 0x24 R/W 0x00000000 GPA Output Enable Register
	volatile unsigned int GPASET; // 0x28 W - OR function on GPA Output Data
	volatile unsigned int GPACLR; // 0x2C W - BIC function on GPA Output Data
	volatile unsigned int GPAXOR; // 0x30 W - XOR function on GPA Output Data

	volatile unsigned int UNDEFINED2[3]; // 34, 38, 3c,
	
	volatile unsigned int GPBDAT; // 0x40 R/W 0x00000000 GPB Data Register
	volatile unsigned int GPBEN; // 0x44 R/W 0x00000000 GPB Output Enable Register
	volatile unsigned int GPBSET; // 0x48 W - OR function on GPB Output Data
	volatile unsigned int GPBCLR; // 0x4C W - BIC function on GPB Output Data
	volatile unsigned int GPBXOR; // 0x50 W - XOR function on GPB Output Data

	volatile unsigned int UNDEFINED3[3]; // 54, 58, 5c,
	
	volatile unsigned int GPCDAT; // 0x60 R/W 0x00000000 GPC Data Register
	volatile unsigned int GPCEN; // 0x64 R/W 0x00000000 GPC Output Enable Register
	volatile unsigned int GPCSET; // 0x68 W - OR function on GPC Output Data
	volatile unsigned int GPCCLR; // 0x6C W - BIC function on GPC Output Data
	volatile unsigned int GPCXOR; // 0x70 W - XOR function on GPC Output Data

	volatile unsigned int UNDEFINED4[3]; // 74, 78, 7c,
	
	volatile unsigned int GPDDAT; // 0x80 R/W 0x00000000 GPD Data Register
	volatile unsigned int GPDEN; // 0x84 R/W 0x00000000 GPD Output Enable Register
	volatile unsigned int GPDSET; // 0x88 W - OR function on GPD Output Data
	volatile unsigned int GPDCLR; // 0x8C W - BIC function on GPD Output Data
	volatile unsigned int GPDXOR; // 0x90 W - XOR function on GPD Output Data

	volatile unsigned int UNDEFINED5[3]; // 94, 98, 9c,
	
	volatile unsigned int GPEDAT; // 0xA0 R/W 0x00000000 GPE Data Register
	volatile unsigned int GPEEN; // 0xA4 R/W 0x00000000 GPE Output Enable Register
	volatile unsigned int GPESET; // 0xA8 W - OR function on GPE Output Data
	volatile unsigned int GPECLR; // 0xAC W - BIC function on GPE Output Data
	volatile unsigned int GPEXOR; // 0xB0 W - XOR function on GPE Output Data

	volatile unsigned int UNDEFINED6[3]; // b4, b8, bc,
		
	volatile unsigned int CPUD0; // 0xC0 R/W Pull-Up/Down Control Register 0
	volatile unsigned int CPUD1; // 0xC4 R/W Pull-Up/Down Control Register 1
	volatile unsigned int CPUD2; // 0xC8 R/W Pull-Up/Down Control Register 2
	volatile unsigned int CPUD3; // 0xCC R/W Pull-Up/Down Control Register 3
	volatile unsigned int CPUD4; // 0xD0 R/W Pull-Up/Down Control Register 4
	volatile unsigned int CPUD5; // 0xD4 R/W Pull-Up/Down Control Register 5
	volatile unsigned int CPUD6; // 0xD8 R/W Pull-Up/Down Control Register 6

	volatile unsigned int UNDEFINED7[1]; // dc,
	
	volatile unsigned int EINTSEL; // 0xE0 R/W 0x03020100 External Interrupt Select Register
} REGISTERGPIO;


typedef struct _REGISTERGSIO // 0xF0057000
{
	volatile unsigned int GSDO0; // 0x00 R/W Unknown GSIO0 Output Data Register
	volatile unsigned int GSDI0; // 0x04 R/W Unknown GSIO0 Input Data Register
	volatile unsigned int GSCR0; // 0x08 R/W 0x0000 GSIO0 Control Register
	volatile unsigned int GSGCR; // 0x0C R/W 0x0000 GSIO Global Control Register
	volatile unsigned int GSDO1; // 0x10 R/W Unknown GSIO1 Output Data Register
	volatile unsigned int GSDI1; // 0x14 R/W Unknown GSIO1 Input Data Register
	volatile unsigned int GSCR1; // 0x18 R/W 0x0000 GSIO1 Control Register
} REGISTERGSIO;


typedef struct _REGISTERI2CCONTROLLER // 0xF0052000
{
	volatile unsigned int PRES0; // 0x00 R/W 0xFFFF Clock Prescale register Master 0
	volatile unsigned int CTRL0; // 0x04 R/W 0x0000 Control Register
	volatile unsigned int TXR0; // 0x08 W 0x0000 Transmit Register
	volatile unsigned int CMD0; // 0x0C W 0x0000 Command Register
	volatile unsigned int RXR0; // 0x10 R 0x0000 Receive Register
	volatile unsigned int SR0; // 0x14 R 0x0000 Status Register
	volatile unsigned int TIME0; // 0x18 R/W 0x0000 Timing Control Register Master 1

	volatile unsigned int UNDEFINED1[9]; // 1c, 20, 24, 28, 2c, 30, 34, 38, 3c,
	
	volatile unsigned int PRES1; // 0x40 R/W 0xFFFF Clock Prescale register
	volatile unsigned int CTRL1; // 0x44 R/W 0x0000 Control Register
	volatile unsigned int TXR1; // 0x48 W 0x0000 Transmit Register
	volatile unsigned int CMD1; // 0x4C W 0x0000 Command Register
	volatile unsigned int RXR1; // 0x50 R 0x0000 Receive Register
	volatile unsigned int SR1; // 0x54 R 0x0000 Status Register
	volatile unsigned int TIME1; // 0x58 R/W 0x0000 Timing Control Register Slave

	volatile unsigned int UNDEFINED2[9]; // 5c, 60, 64, 68, 6c, 70, 74, 78, 7c,
	
	volatile unsigned int PORT; // 0x80 R/W - Data Access port (TX/RX FIFO)
	volatile unsigned int CTL; // 0x84 R/W 0x00000000 Control register
	volatile unsigned int ADDR; // 0x88 W 0x00000000 Address register
	volatile unsigned int INT; // 0x8C W 0x00000000 Interrupt Enable Register
	volatile unsigned int STAT; // 0x90 R 0x00000000 Status Register

	volatile unsigned int UNDEFINED3[2]; // 94, 98, 

	volatile unsigned int MBF; // 0x9C R/W 0x00000000 Buffer Valid Flag
	volatile unsigned int MB0; // 0xA0 R/W 0x00000000 Data Buffer 0 (Byte 3 ~ 0)
	volatile unsigned int MB1; // 0xA4 R/W 0x00000000 Data Buffer 1 (Byte 7 ~ 4)

	volatile unsigned int UNDEFINED4[6]; // a8, ac, b0, b4, b8, bc, 

	volatile unsigned int IRQSTR; // 0xC0 R 0x00000000 IRQ Status Register Status
} REGISTERI2CCONTROLLER;


#define BITSET(X, MASK)				( (X) |= (UINT)(MASK) )
#define	BITSCLR(X, SMASK, CMASK)	( (X) = ((((UINT)(X)) | ((UINT)(SMASK))) & ~((UINT)(CMASK))) )
#define	BITCSET(X, CMASK, SMASK)	( (X) = ((((UINT)(X)) & ~((UINT)(CMASK))) | ((UINT)(SMASK))) )
#define	BITCLR(X, MASK)				( (X) &= ~((UINT)(MASK)) )
#define	BITXOR(X, MASK)				( (X) ^= (UINT)(MASK) )


#ifdef __cplusplus
}
#endif

#endif//__TCC78XWINCE_H__