clock.map.rpt

用VHDL开发的数字钟资料 完整的实验代码

Info: Elaborating entity "divide" for hierarchy "divide:u1"
Info: Elaborating entity "time" for hierarchy "time:u2"
Info: Elaborating entity "led" for hierarchy "led:u3"
Warning (10631): VHDL Process Statement warning at led.vhd(48): inferring latch(es) for signal or variable "d1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at led.vhd(48): inferring latch(es) for signal or variable "d", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at led.vhd(77): inferring latch(es) for signal or variable "c1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at led.vhd(77): inferring latch(es) for signal or variable "c", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at led.vhd(106): inferring latch(es) for signal or variable "b1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at led.vhd(106): inferring latch(es) for signal or variable "b", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "b[0]" at led.vhd(106)
Info (10041): Inferred latch for "b[1]" at led.vhd(106)
Info (10041): Inferred latch for "b[2]" at led.vhd(106)
Info (10041): Inferred latch for "b[3]" at led.vhd(106)
Info (10041): Inferred latch for "b[4]" at led.vhd(106)
Info (10041): Inferred latch for "b[5]" at led.vhd(106)
Info (10041): Inferred latch for "b[6]" at led.vhd(106)
Info (10041): Inferred latch for "b1[0]" at led.vhd(106)
Info (10041): Inferred latch for "b1[1]" at led.vhd(106)
Info (10041): Inferred latch for "b1[2]" at led.vhd(106)
Info (10041): Inferred latch for "b1[3]" at led.vhd(106)
Info (10041): Inferred latch for "b1[4]" at led.vhd(106)
Info (10041): Inferred latch for "b1[5]" at led.vhd(106)
Info (10041): Inferred latch for "b1[6]" at led.vhd(106)
Info (10041): Inferred latch for "c[0]" at led.vhd(77)
Info (10041): Inferred latch for "c[1]" at led.vhd(77)
Info (10041): Inferred latch for "c[2]" at led.vhd(77)
Info (10041): Inferred latch for "c[3]" at led.vhd(77)
Info (10041): Inferred latch for "c[4]" at led.vhd(77)
Info (10041): Inferred latch for "c[5]" at led.vhd(77)
Info (10041): Inferred latch for "c[6]" at led.vhd(77)
Info (10041): Inferred latch for "c1[0]" at led.vhd(77)
Info (10041): Inferred latch for "c1[1]" at led.vhd(77)
Info (10041): Inferred latch for "c1[2]" at led.vhd(77)
Info (10041): Inferred latch for "c1[3]" at led.vhd(77)
Info (10041): Inferred latch for "c1[4]" at led.vhd(77)
Info (10041): Inferred latch for "c1[5]" at led.vhd(77)
Info (10041): Inferred latch for "c1[6]" at led.vhd(77)
Info (10041): Inferred latch for "d[0]" at led.vhd(48)
Info (10041): Inferred latch for "d[1]" at led.vhd(48)
Info (10041): Inferred latch for "d[2]" at led.vhd(48)
Info (10041): Inferred latch for "d[3]" at led.vhd(48)
Info (10041): Inferred latch for "d[4]" at led.vhd(48)
Info (10041): Inferred latch for "d[5]" at led.vhd(48)
Info (10041): Inferred latch for "d[6]" at led.vhd(48)
Info (10041): Inferred latch for "d1[0]" at led.vhd(48)
Info (10041): Inferred latch for "d1[1]" at led.vhd(48)
Info (10041): Inferred latch for "d1[2]" at led.vhd(48)
Info (10041): Inferred latch for "d1[3]" at led.vhd(48)
Info (10041): Inferred latch for "d1[4]" at led.vhd(48)
Info (10041): Inferred latch for "d1[5]" at led.vhd(48)
Info (10041): Inferred latch for "d1[6]" at led.vhd(48)
Info: Inferred 2 megafunctions from design logic
    Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "divide:u1|Add0"
    Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "time:u2|Add4"
Info: Elaborated megafunction instantiation "divide:u1|lpm_add_sub:Add0"
Info: Instantiated megafunction "divide:u1|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "20"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "divide:u1|lpm_add_sub:Add0|addcore:adder", which is child of megafunction instantiation "divide:u1|lpm_add_sub:Add0"
Info: Elaborated megafunction instantiation "divide:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "divide:u1|lpm_add_sub:Add0"
Info: Elaborated megafunction instantiation "divide:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "divide:u1|lpm_add_sub:Add0"
Info: Elaborated megafunction instantiation "divide:u1|lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "divide:u1|lpm_add_sub:Add0"
Info: Elaborated megafunction instantiation "divide:u1|lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "divide:u1|lpm_add_sub:Add0"
Info: Elaborated megafunction instantiation "time:u2|lpm_add_sub:Add4"
Info: Instantiated megafunction "time:u2|lpm_add_sub:Add4" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Elaborated megafunction instantiation "time:u2|lpm_add_sub:Add4|addcore:adder", which is child of megafunction instantiation "time:u2|lpm_add_sub:Add4"
Info: Elaborated megafunction instantiation "time:u2|lpm_add_sub:Add4|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "time:u2|lpm_add_sub:Add4"
Info: Elaborated megafunction instantiation "time:u2|lpm_add_sub:Add4|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "time:u2|lpm_add_sub:Add4"
Info: Elaborated megafunction instantiation "time:u2|lpm_add_sub:Add4|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "time:u2|lpm_add_sub:Add4"
Warning: Latch led:u3|b[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|a[1]
Warning: Latch led:u3|b1[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|b[1]
Warning: Latch led:u3|c[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|c[1]
Warning: Latch led:u3|c1[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|d[1]
Warning: Latch led:u3|d[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|e[1]
Warning: Latch led:u3|d1[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|f[1]
Warning: Latch led:u3|b[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|a[2]
Warning: Latch led:u3|b1[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|b[2]
Warning: Latch led:u3|c[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|c[2]
Warning: Latch led:u3|c1[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|d[2]
Warning: Latch led:u3|d[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|e[2]
Warning: Latch led:u3|d1[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|f[2]
Warning: Latch led:u3|b[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|a[1]
Warning: Latch led:u3|b1[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|b[1]
Warning: Latch led:u3|c[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|c[1]
Warning: Latch led:u3|c1[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|d[1]
Warning: Latch led:u3|d[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|e[1]
Warning: Latch led:u3|d1[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|f[1]
Warning: Latch led:u3|b[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|a[1]
Warning: Latch led:u3|b1[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|b[1]
Warning: Latch led:u3|c[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|c[1]
Warning: Latch led:u3|c1[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|d[1]
Warning: Latch led:u3|d[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|e[1]
Warning: Latch led:u3|d1[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|f[1]
Warning: Latch led:u3|b[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|a[1]
Warning: Latch led:u3|b1[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|b[1]
Warning: Latch led:u3|c[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|c[1]
Warning: Latch led:u3|c1[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|d[1]
Warning: Latch led:u3|d[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|e[1]
Warning: Latch led:u3|d1[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|f[1]
Warning: Latch led:u3|b[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|a[1]
Warning: Latch led:u3|b1[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|b[1]
Warning: Latch led:u3|c[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|c[1]
Warning: Latch led:u3|c1[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|d[1]
Warning: Latch led:u3|d[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|e[1]
Warning: Latch led:u3|d1[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|f[1]
Warning: Latch led:u3|b[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|a[1]
Warning: Latch led:u3|b1[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|b[1]
Warning: Latch led:u3|c[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|c[1]
Warning: Latch led:u3|c1[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|d[1]
Warning: Latch led:u3|d[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|e[1]
Warning: Latch led:u3|d1[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal time:u2|f[1]
Info: Implemented 270 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 11 output pins
    Info: Implemented 255 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 91 warnings
    Info: Peak virtual memory: 180 megabytes
    Info: Processing ended: Thu Apr 23 11:39:56 2009
    Info: Elapsed time: 00:00:07
    Info: Total CPU time (on all processors): 00:00:03