📄 clock.map.rpt
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; |a_csnbuffer:result_node| ; 18 (18) ; 0 ; 0 ; 0 ; 18 (18) ; 0 (0) ; 0 (0) ; 18 (18) ; 0 (0) ; |clock|divide:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node ; work ;
; |led:u3| ; 118 (118) ; 3 ; 0 ; 0 ; 115 (115) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |clock|led:u3 ; work ;
; |time:u2| ; 74 (70) ; 26 ; 0 ; 0 ; 48 (44) ; 4 (4) ; 22 (22) ; 4 (0) ; 0 (0) ; |clock|time:u2 ; work ;
; |lpm_add_sub:Add4| ; 4 (0) ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 0 (0) ; 4 (0) ; 0 (0) ; |clock|time:u2|lpm_add_sub:Add4 ; work ;
; |addcore:adder| ; 4 (1) ; 0 ; 0 ; 0 ; 4 (1) ; 0 (0) ; 0 (0) ; 4 (1) ; 0 (0) ; |clock|time:u2|lpm_add_sub:Add4|addcore:adder ; work ;
; |a_csnbuffer:result_node| ; 3 (3) ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; 3 (3) ; 0 (0) ; |clock|time:u2|lpm_add_sub:Add4|addcore:adder|a_csnbuffer:result_node ; work ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; led:u3|b[0] ; led:u3|Mux9 ; yes ;
; led:u3|b1[0] ; led:u3|Mux16 ; yes ;
; led:u3|c[0] ; led:u3|Mux24 ; yes ;
; led:u3|c1[0] ; led:u3|Mux32 ; yes ;
; led:u3|d[0] ; led:u3|Mux40 ; yes ;
; led:u3|d1[0] ; led:u3|Mux48 ; yes ;
; led:u3|b[1] ; led:u3|Mux9 ; yes ;
; led:u3|b1[1] ; led:u3|Mux16 ; yes ;
; led:u3|c[1] ; led:u3|Mux24 ; yes ;
; led:u3|c1[1] ; led:u3|Mux32 ; yes ;
; led:u3|d[1] ; led:u3|Mux40 ; yes ;
; led:u3|d1[1] ; led:u3|Mux48 ; yes ;
; led:u3|b[2] ; led:u3|Mux9 ; yes ;
; led:u3|b1[2] ; led:u3|Mux16 ; yes ;
; led:u3|c[2] ; led:u3|Mux24 ; yes ;
; led:u3|c1[2] ; led:u3|Mux32 ; yes ;
; led:u3|d[2] ; led:u3|Mux40 ; yes ;
; led:u3|d1[2] ; led:u3|Mux48 ; yes ;
; led:u3|b[3] ; led:u3|Mux9 ; yes ;
; led:u3|b1[3] ; led:u3|Mux16 ; yes ;
; led:u3|c[3] ; led:u3|Mux24 ; yes ;
; led:u3|c1[3] ; led:u3|Mux32 ; yes ;
; led:u3|d[3] ; led:u3|Mux40 ; yes ;
; led:u3|d1[3] ; led:u3|Mux48 ; yes ;
; led:u3|b[4] ; led:u3|Mux9 ; yes ;
; led:u3|b1[4] ; led:u3|Mux16 ; yes ;
; led:u3|c[4] ; led:u3|Mux24 ; yes ;
; led:u3|c1[4] ; led:u3|Mux32 ; yes ;
; led:u3|d[4] ; led:u3|Mux40 ; yes ;
; led:u3|d1[4] ; led:u3|Mux48 ; yes ;
; led:u3|b[5] ; led:u3|Mux9 ; yes ;
; led:u3|b1[5] ; led:u3|Mux16 ; yes ;
; led:u3|c[5] ; led:u3|Mux24 ; yes ;
; led:u3|c1[5] ; led:u3|Mux32 ; yes ;
; led:u3|d[5] ; led:u3|Mux40 ; yes ;
; led:u3|d1[5] ; led:u3|Mux48 ; yes ;
; led:u3|b[6] ; led:u3|Mux9 ; yes ;
; led:u3|b1[6] ; led:u3|Mux16 ; yes ;
; led:u3|c[6] ; led:u3|Mux24 ; yes ;
; led:u3|c1[6] ; led:u3|Mux32 ; yes ;
; led:u3|d[6] ; led:u3|Mux40 ; yes ;
; led:u3|d1[6] ; led:u3|Mux48 ; yes ;
; Number of user-specified and inferred latches = 42 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 50 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 24 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 22 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------------------+
; Source assignments for divide:u1|lpm_add_sub:Add0|addcore:adder ;
+---------------------------+-------+------+----------------------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+----------------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103 ; - ; - ;
+---------------------------+-------+------+----------------------+
+---------------------------------------------------------------+
; Source assignments for time:u2|lpm_add_sub:Add4|addcore:adder ;
+---------------------------+-------+------+--------------------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+--------------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103 ; - ; - ;
+---------------------------+-------+------+--------------------+
+-----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: divide:u1|lpm_add_sub:Add0 ;
+------------------------+-------------+--------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+--------------------------------------+
; LPM_WIDTH ; 20 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 1 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_poh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: time:u2|lpm_add_sub:Add4 ;
+------------------------+-------------+------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+------------------------------------+
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 1 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_njh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
Info: Processing started: Thu Apr 23 11:39:49 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 2 design units, including 1 entities, in source file clock.vhd
Info: Found design unit 1: clock-one
Info: Found entity 1: clock
Info: Found 2 design units, including 1 entities, in source file time.vhd
Info: Found design unit 1: time-one
Info: Found entity 1: time
Info: Found 2 design units, including 1 entities, in source file led.vhd
Info: Found design unit 1: led-one
Info: Found entity 1: led
Warning: Entity "divide" obtained from "G:/edatest/yulin/yulin/clock/clock/divide.vhd" instead of from Quartus II megafunction library
Info: Found 2 design units, including 1 entities, in source file divide.vhd
Info: Found design unit 1: divide-one
Info: Found entity 1: divide
Info: Elaborating entity "clock" for the top level hierarchy
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