time.tan.qmsg

用VHDL开发的数字钟资料 完整的实验代码

{ "Info" "ITDB_FULL_TCO_RESULT" "clk h\[3\] e\[3\] 24.900 ns register " "Info: tco from clock \"clk\" to destination pin \"h\[3\]\" through register \"e\[3\]\" is 24.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 16.100 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 16.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns cmin 2 REG LC1_C13 10 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C13; Fanout = 10; REG Node = 'cmin'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clk cmin } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(1.100 ns) 12.100 ns chour 3 REG LC3_C5 9 " "Info: 3: + IC(4.600 ns) + CELL(1.100 ns) = 12.100 ns; Loc. = LC3_C5; Fanout = 9; REG Node = 'chour'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { cmin chour } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.000 ns) 16.100 ns e\[3\] 4 REG LC4_B17 6 " "Info: 4: + IC(4.000 ns) + CELL(0.000 ns) = 16.100 ns; Loc. = LC4_B17; Fanout = 6; REG Node = 'e\[3\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { chour e[3] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 31.06 % ) " "Info: Total cell delay = 5.000 ns ( 31.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.100 ns ( 68.94 % ) " "Info: Total interconnect delay = 11.100 ns ( 68.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "16.100 ns" { clk cmin chour e[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "16.100 ns" { clk {} clk~out {} cmin {} chour {} e[3] {} } { 0.000ns 0.000ns 2.500ns 4.600ns 4.000ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.700 ns + Longest register pin " "Info: + Longest register to pin delay is 7.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns e\[3\] 1 REG LC4_B17 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B17; Fanout = 6; REG Node = 'e\[3\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { e[3] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(5.100 ns) 7.700 ns h\[3\] 2 PIN PIN_23 0 " "Info: 2: + IC(2.600 ns) + CELL(5.100 ns) = 7.700 ns; Loc. = PIN_23; Fanout = 0; PIN Node = 'h\[3\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "7.700 ns" { e[3] h[3] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 66.23 % ) " "Info: Total cell delay = 5.100 ns ( 66.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 33.77 % ) " "Info: Total interconnect delay = 2.600 ns ( 33.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "7.700 ns" { e[3] h[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "7.700 ns" { e[3] {} h[3] {} } { 0.000ns 2.600ns } { 0.000ns 5.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "16.100 ns" { clk cmin chour e[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "16.100 ns" { clk {} clk~out {} cmin {} chour {} e[3] {} } { 0.000ns 0.000ns 2.500ns 4.600ns 4.000ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "7.700 ns" { e[3] h[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "7.700 ns" { e[3] {} h[3] {} } { 0.000ns 2.600ns } { 0.000ns 5.100ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "e\[0\] en clk 11.900 ns register " "Info: th for register \"e\[0\]\" (data pin = \"en\", clock pin = \"clk\") is 11.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 16.100 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 16.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns cmin 2 REG LC1_C13 10 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C13; Fanout = 10; REG Node = 'cmin'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clk cmin } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(1.100 ns) 12.100 ns chour 3 REG LC3_C5 9 " "Info: 3: + IC(4.600 ns) + CELL(1.100 ns) = 12.100 ns; Loc. = LC3_C5; Fanout = 9; REG Node = 'chour'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { cmin chour } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.000 ns) 16.100 ns e\[0\] 4 REG LC3_B16 8 " "Info: 4: + IC(4.000 ns) + CELL(0.000 ns) = 16.100 ns; Loc. = LC3_B16; Fanout = 8; REG Node = 'e\[0\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { chour e[0] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 31.06 % ) " "Info: Total cell delay = 5.000 ns ( 31.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.100 ns ( 68.94 % ) " "Info: Total interconnect delay = 11.100 ns ( 68.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "16.100 ns" { clk cmin chour e[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "16.100 ns" { clk {} clk~out {} cmin {} chour {} e[0] {} } { 0.000ns 0.000ns 2.500ns 4.600ns 4.000ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns en 1 PIN PIN_44 12 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_44; Fanout = 12; PIN Node = 'en'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.200 ns) 5.800 ns e\[0\] 2 REG LC3_B16 8 " "Info: 2: + IC(1.800 ns) + CELL(1.200 ns) = 5.800 ns; Loc. = LC3_B16; Fanout = 8; REG Node = 'e\[0\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { en e[0] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 68.97 % ) " "Info: Total cell delay = 4.000 ns ( 68.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns ( 31.03 % ) " "Info: Total interconnect delay = 1.800 ns ( 31.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { en e[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.800 ns" { en {} en~out {} e[0] {} } { 0.000ns 0.000ns 1.800ns } { 0.000ns 2.800ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "16.100 ns" { clk cmin chour e[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "16.100 ns" { clk {} clk~out {} cmin {} chour {} e[0] {} } { 0.000ns 0.000ns 2.500ns 4.600ns 4.000ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { en e[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.800 ns" { en {} en~out {} e[0] {} } { 0.000ns 0.000ns 1.800ns } { 0.000ns 2.800ns 1.200ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_UNUSED" "" "Info: Parallel compilation was enabled but no parallel operations were performed" {  } {  } 0 0 "Parallel compilation was enabled but no parallel operations were performed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "124 " "Info: Peak virtual memory: 124 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 22 22:11:57 2009 " "Info: Processing ended: Wed Apr 22 22:11:57 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}