time.tan.qmsg

用VHDL开发的数字钟资料 完整的实验代码

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 8 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "chour " "Info: Detected ripple clock \"chour\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 21 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "chour" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cmin " "Info: Detected ripple clock \"cmin\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 20 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "cmin" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register e\[0\] register f\[3\] 53.76 MHz 18.6 ns Internal " "Info: Clock \"clk\" has Internal fmax of 53.76 MHz between source register \"e\[0\]\" and destination register \"f\[3\]\" (period= 18.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.900 ns + Longest register register " "Info: + Longest register to register delay is 14.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns e\[0\] 1 REG LC3_B16 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B16; Fanout = 8; REG Node = 'e\[0\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { e[0] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.800 ns) 4.200 ns LessThan5~48 2 COMB LC2_B17 4 " "Info: 2: + IC(2.400 ns) + CELL(1.800 ns) = 4.200 ns; Loc. = LC2_B17; Fanout = 4; COMB Node = 'LessThan5~48'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.200 ns" { e[0] LessThan5~48 } "NODE_NAME" } } { "e:/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.800 ns) 8.100 ns f\[0\]~348 3 COMB LC6_B16 2 " "Info: 3: + IC(2.100 ns) + CELL(1.800 ns) = 8.100 ns; Loc. = LC6_B16; Fanout = 2; COMB Node = 'f\[0\]~348'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { LessThan5~48 f[0]~348 } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 11.000 ns f\[0\]~349 4 COMB LC2_B16 4 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 11.000 ns; Loc. = LC2_B16; Fanout = 4; COMB Node = 'f\[0\]~349'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { f[0]~348 f[0]~349 } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 14.900 ns f\[3\] 5 REG LC7_B13 8 " "Info: 5: + IC(2.200 ns) + CELL(1.700 ns) = 14.900 ns; Loc. = LC7_B13; Fanout = 8; REG Node = 'f\[3\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { f[0]~349 f[3] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.600 ns ( 51.01 % ) " "Info: Total cell delay = 7.600 ns ( 51.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.300 ns ( 48.99 % ) " "Info: Total interconnect delay = 7.300 ns ( 48.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "14.900 ns" { e[0] LessThan5~48 f[0]~348 f[0]~349 f[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "14.900 ns" { e[0] {} LessThan5~48 {} f[0]~348 {} f[0]~349 {} f[3] {} } { 0.000ns 2.400ns 2.100ns 0.600ns 2.200ns } { 0.000ns 1.800ns 1.800ns 2.300ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.100 ns - Smallest " "Info: - Smallest clock skew is -0.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 16.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 16.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns cmin 2 REG LC1_C13 10 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C13; Fanout = 10; REG Node = 'cmin'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clk cmin } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(1.100 ns) 12.100 ns chour 3 REG LC3_C5 9 " "Info: 3: + IC(4.600 ns) + CELL(1.100 ns) = 12.100 ns; Loc. = LC3_C5; Fanout = 9; REG Node = 'chour'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { cmin chour } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(0.000 ns) 16.000 ns f\[3\] 4 REG LC7_B13 8 " "Info: 4: + IC(3.900 ns) + CELL(0.000 ns) = 16.000 ns; Loc. = LC7_B13; Fanout = 8; REG Node = 'f\[3\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { chour f[3] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 31.25 % ) " "Info: Total cell delay = 5.000 ns ( 31.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.000 ns ( 68.75 % ) " "Info: Total interconnect delay = 11.000 ns ( 68.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "16.000 ns" { clk cmin chour f[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "16.000 ns" { clk {} clk~out {} cmin {} chour {} f[3] {} } { 0.000ns 0.000ns 2.500ns 4.600ns 3.900ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 16.100 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 16.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns cmin 2 REG LC1_C13 10 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C13; Fanout = 10; REG Node = 'cmin'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clk cmin } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(1.100 ns) 12.100 ns chour 3 REG LC3_C5 9 " "Info: 3: + IC(4.600 ns) + CELL(1.100 ns) = 12.100 ns; Loc. = LC3_C5; Fanout = 9; REG Node = 'chour'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { cmin chour } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.000 ns) 16.100 ns e\[0\] 4 REG LC3_B16 8 " "Info: 4: + IC(4.000 ns) + CELL(0.000 ns) = 16.100 ns; Loc. = LC3_B16; Fanout = 8; REG Node = 'e\[0\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { chour e[0] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 31.06 % ) " "Info: Total cell delay = 5.000 ns ( 31.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.100 ns ( 68.94 % ) " "Info: Total interconnect delay = 11.100 ns ( 68.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "16.100 ns" { clk cmin chour e[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "16.100 ns" { clk {} clk~out {} cmin {} chour {} e[0] {} } { 0.000ns 0.000ns 2.500ns 4.600ns 4.000ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "16.000 ns" { clk cmin chour f[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "16.000 ns" { clk {} clk~out {} cmin {} chour {} f[3] {} } { 0.000ns 0.000ns 2.500ns 4.600ns 3.900ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "16.100 ns" { clk cmin chour e[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "16.100 ns" { clk {} clk~out {} cmin {} chour {} e[0] {} } { 0.000ns 0.000ns 2.500ns 4.600ns 4.000ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "14.900 ns" { e[0] LessThan5~48 f[0]~348 f[0]~349 f[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "14.900 ns" { e[0] {} LessThan5~48 {} f[0]~348 {} f[0]~349 {} f[3] {} } { 0.000ns 2.400ns 2.100ns 0.600ns 2.200ns } { 0.000ns 1.800ns 1.800ns 2.300ns 1.700ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "16.000 ns" { clk cmin chour f[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "16.000 ns" { clk {} clk~out {} cmin {} chour {} f[3] {} } { 0.000ns 0.000ns 2.500ns 4.600ns 3.900ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "16.100 ns" { clk cmin chour e[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "16.100 ns" { clk {} clk~out {} cmin {} chour {} e[0] {} } { 0.000ns 0.000ns 2.500ns 4.600ns 4.000ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "b\[1\] en clk 10.500 ns register " "Info: tsu for register \"b\[1\]\" (data pin = \"en\", clock pin = \"clk\") is 10.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.300 ns + Longest pin register " "Info: + Longest pin to register delay is 13.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns en 1 PIN PIN_44 12 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_44; Fanout = 12; PIN Node = 'en'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.300 ns) 6.900 ns b\[0\]~218 2 COMB LC6_C13 4 " "Info: 2: + IC(1.800 ns) + CELL(2.300 ns) = 6.900 ns; Loc. = LC6_C13; Fanout = 4; COMB Node = 'b\[0\]~218'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.100 ns" { en b[0]~218 } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.300 ns) 11.500 ns b\[1\]~219 3 COMB LC3_C19 2 " "Info: 3: + IC(2.300 ns) + CELL(2.300 ns) = 11.500 ns; Loc. = LC3_C19; Fanout = 2; COMB Node = 'b\[1\]~219'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { b[0]~218 b[1]~219 } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 13.300 ns b\[1\] 4 REG LC7_C19 6 " "Info: 4: + IC(0.600 ns) + CELL(1.200 ns) = 13.300 ns; Loc. = LC7_C19; Fanout = 6; REG Node = 'b\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { b[1]~219 b[1] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.600 ns ( 64.66 % ) " "Info: Total cell delay = 8.600 ns ( 64.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.700 ns ( 35.34 % ) " "Info: Total interconnect delay = 4.700 ns ( 35.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "13.300 ns" { en b[0]~218 b[1]~219 b[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "13.300 ns" { en {} en~out {} b[0]~218 {} b[1]~219 {} b[1] {} } { 0.000ns 0.000ns 1.800ns 2.300ns 0.600ns } { 0.000ns 2.800ns 2.300ns 2.300ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns b\[1\] 2 REG LC7_C19 6 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_C19; Fanout = 6; REG Node = 'b\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { clk b[1] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/time/time.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk b[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} b[1] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "13.300 ns" { en b[0]~218 b[1]~219 b[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "13.300 ns" { en {} en~out {} b[0]~218 {} b[1]~219 {} b[1] {} } { 0.000ns 0.000ns 1.800ns 2.300ns 0.600ns } { 0.000ns 2.800ns 2.300ns 2.300ns 1.200ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk b[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} b[1] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}