time.tan.rpt

用VHDL开发的数字钟资料 完整的实验代码

; N/A           ; None        ; 9.000 ns  ; en   ; e[2]  ; clk      ;
; N/A           ; None        ; 9.000 ns  ; en   ; f[2]  ; clk      ;
; N/A           ; None        ; 7.800 ns  ; en   ; f[0]  ; clk      ;
; N/A           ; None        ; 7.300 ns  ; en   ; f[3]  ; clk      ;
; N/A           ; None        ; 7.300 ns  ; en   ; f[1]  ; clk      ;
; N/A           ; None        ; 6.900 ns  ; en   ; c[0]  ; clk      ;
; N/A           ; None        ; 6.900 ns  ; en   ; c[3]  ; clk      ;
; N/A           ; None        ; 4.500 ns  ; en   ; c[1]  ; clk      ;
; N/A           ; None        ; 4.500 ns  ; en   ; c[2]  ; clk      ;
; N/A           ; None        ; 4.100 ns  ; rst  ; chour ; clk      ;
; N/A           ; None        ; 2.900 ns  ; en   ; d[0]  ; clk      ;
; N/A           ; None        ; 2.900 ns  ; en   ; d[2]  ; clk      ;
; N/A           ; None        ; 2.100 ns  ; en   ; chour ; clk      ;
; N/A           ; None        ; 1.200 ns  ; en   ; a[0]  ; clk      ;
; N/A           ; None        ; 1.100 ns  ; en   ; a[3]  ; clk      ;
; N/A           ; None        ; 0.000 ns  ; en   ; d[1]  ; clk      ;
; N/A           ; None        ; 0.000 ns  ; en   ; d[3]  ; clk      ;
; N/A           ; None        ; -1.700 ns ; rst  ; cmin  ; clk      ;
; N/A           ; None        ; -1.700 ns ; en   ; a[1]  ; clk      ;
; N/A           ; None        ; -1.700 ns ; en   ; a[2]  ; clk      ;
; N/A           ; None        ; -1.800 ns ; en   ; b[0]  ; clk      ;
; N/A           ; None        ; -3.500 ns ; en   ; b[2]  ; clk      ;
; N/A           ; None        ; -4.200 ns ; en   ; cmin  ; clk      ;
; N/A           ; None        ; -6.400 ns ; en   ; b[1]  ; clk      ;
; N/A           ; None        ; -6.400 ns ; en   ; b[3]  ; clk      ;
+---------------+-------------+-----------+------+-------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Wed Apr 22 22:11:52 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off time -c time
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "chour" as buffer
    Info: Detected ripple clock "cmin" as buffer
Info: Clock "clk" has Internal fmax of 53.76 MHz between source register "e[0]" and destination register "f[3]" (period= 18.6 ns)
    Info: + Longest register to register delay is 14.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B16; Fanout = 8; REG Node = 'e[0]'
        Info: 2: + IC(2.400 ns) + CELL(1.800 ns) = 4.200 ns; Loc. = LC2_B17; Fanout = 4; COMB Node = 'LessThan5~48'
        Info: 3: + IC(2.100 ns) + CELL(1.800 ns) = 8.100 ns; Loc. = LC6_B16; Fanout = 2; COMB Node = 'f[0]~348'
        Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 11.000 ns; Loc. = LC2_B16; Fanout = 4; COMB Node = 'f[0]~349'
        Info: 5: + IC(2.200 ns) + CELL(1.700 ns) = 14.900 ns; Loc. = LC7_B13; Fanout = 8; REG Node = 'f[3]'
        Info: Total cell delay = 7.600 ns ( 51.01 % )
        Info: Total interconnect delay = 7.300 ns ( 48.99 % )
    Info: - Smallest clock skew is -0.100 ns
        Info: + Shortest clock path from clock "clk" to destination register is 16.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C13; Fanout = 10; REG Node = 'cmin'
            Info: 3: + IC(4.600 ns) + CELL(1.100 ns) = 12.100 ns; Loc. = LC3_C5; Fanout = 9; REG Node = 'chour'
            Info: 4: + IC(3.900 ns) + CELL(0.000 ns) = 16.000 ns; Loc. = LC7_B13; Fanout = 8; REG Node = 'f[3]'
            Info: Total cell delay = 5.000 ns ( 31.25 % )
            Info: Total interconnect delay = 11.000 ns ( 68.75 % )
        Info: - Longest clock path from clock "clk" to source register is 16.100 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C13; Fanout = 10; REG Node = 'cmin'
            Info: 3: + IC(4.600 ns) + CELL(1.100 ns) = 12.100 ns; Loc. = LC3_C5; Fanout = 9; REG Node = 'chour'
            Info: 4: + IC(4.000 ns) + CELL(0.000 ns) = 16.100 ns; Loc. = LC3_B16; Fanout = 8; REG Node = 'e[0]'
            Info: Total cell delay = 5.000 ns ( 31.06 % )
            Info: Total interconnect delay = 11.100 ns ( 68.94 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 2.500 ns
Info: tsu for register "b[1]" (data pin = "en", clock pin = "clk") is 10.500 ns
    Info: + Longest pin to register delay is 13.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_44; Fanout = 12; PIN Node = 'en'
        Info: 2: + IC(1.800 ns) + CELL(2.300 ns) = 6.900 ns; Loc. = LC6_C13; Fanout = 4; COMB Node = 'b[0]~218'
        Info: 3: + IC(2.300 ns) + CELL(2.300 ns) = 11.500 ns; Loc. = LC3_C19; Fanout = 2; COMB Node = 'b[1]~219'
        Info: 4: + IC(0.600 ns) + CELL(1.200 ns) = 13.300 ns; Loc. = LC7_C19; Fanout = 6; REG Node = 'b[1]'
        Info: Total cell delay = 8.600 ns ( 64.66 % )
        Info: Total interconnect delay = 4.700 ns ( 35.34 % )
    Info: + Micro setup delay of destination is 2.500 ns
    Info: - Shortest clock path from clock "clk" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_C19; Fanout = 6; REG Node = 'b[1]'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: tco from clock "clk" to destination pin "h[3]" through register "e[3]" is 24.900 ns
    Info: + Longest clock path from clock "clk" to source register is 16.100 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C13; Fanout = 10; REG Node = 'cmin'
        Info: 3: + IC(4.600 ns) + CELL(1.100 ns) = 12.100 ns; Loc. = LC3_C5; Fanout = 9; REG Node = 'chour'
        Info: 4: + IC(4.000 ns) + CELL(0.000 ns) = 16.100 ns; Loc. = LC4_B17; Fanout = 6; REG Node = 'e[3]'
        Info: Total cell delay = 5.000 ns ( 31.06 % )
        Info: Total interconnect delay = 11.100 ns ( 68.94 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 7.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B17; Fanout = 6; REG Node = 'e[3]'
        Info: 2: + IC(2.600 ns) + CELL(5.100 ns) = 7.700 ns; Loc. = PIN_23; Fanout = 0; PIN Node = 'h[3]'
        Info: Total cell delay = 5.100 ns ( 66.23 % )
        Info: Total interconnect delay = 2.600 ns ( 33.77 % )
Info: th for register "e[0]" (data pin = "en", clock pin = "clk") is 11.900 ns
    Info: + Longest clock path from clock "clk" to destination register is 16.100 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C13; Fanout = 10; REG Node = 'cmin'
        Info: 3: + IC(4.600 ns) + CELL(1.100 ns) = 12.100 ns; Loc. = LC3_C5; Fanout = 9; REG Node = 'chour'
        Info: 4: + IC(4.000 ns) + CELL(0.000 ns) = 16.100 ns; Loc. = LC3_B16; Fanout = 8; REG Node = 'e[0]'
        Info: Total cell delay = 5.000 ns ( 31.06 % )
        Info: Total interconnect delay = 11.100 ns ( 68.94 % )
    Info: + Micro hold delay of destination is 1.600 ns
    Info: - Shortest pin to register delay is 5.800 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_44; Fanout = 12; PIN Node = 'en'
        Info: 2: + IC(1.800 ns) + CELL(1.200 ns) = 5.800 ns; Loc. = LC3_B16; Fanout = 8; REG Node = 'e[0]'
        Info: Total cell delay = 4.000 ns ( 68.97 % )
        Info: Total interconnect delay = 1.800 ns ( 31.03 % )
Info: Parallel compilation was enabled but no parallel operations were performed
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 124 megabytes
    Info: Processing ended: Wed Apr 22 22:11:57 2009
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:01