ether.c

嵌入式试验箱S3C2410的bootloader源代码

	 * Enter Command:  Initialize Tx Params for SCC
	 */

	do {				/* Spin until ready to issue command    */
		__asm__ ("eieio");
	} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
	/* Issue command */
	immr->im_cpm.cp_cpcr =
			((CPM_CR_INIT_TX << 8) | (cpm_cr[scc_index] << 4) |
			 CPM_CR_FLG);
	do {				/* Spin until command processed     */
		__asm__ ("eieio");
	} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);

	/*
	 * Mask all Events in SCCM - we use polling mode
	 */
	immr->im_cpm.cp_scc[scc_index].scc_sccm = 0;

	/*
	 * Clear Events in SCCE -- Clear bits by writing 1's
	 */

	immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0);


	/*
	 * Initialize GSMR High 32-Bits
	 * Settings:  Normal Mode
	 */

	immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0;

	/*
	 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
	 * Settings:
	 *     TCI = Invert
	 *     TPL =  48 bits
	 *     TPP = Repeating 10's
	 *     LOOP = Loopback
	 *     MODE = Ethernet
	 */

	immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI |
						    SCC_GSMRL_TPL_48 |
						    SCC_GSMRL_TPP_10 |
						    SCC_GSMRL_DIAG_LOOP |
						    SCC_GSMRL_MODE_ENET);

	/*
	 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
	 */

	immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555;

	/*
	 * Initialize the PSMR
	 * Settings:
	 *  CRC = 32-Bit CCITT
	 *  NIB = Begin searching for SFD 22 bits after RENA
	 *  LPB = Loopback Enable (Needed when FDE is set)
	 */
	immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC |
			SCC_PSMR_NIB22 | SCC_PSMR_LPB;

#if 0
	/*
	 * Configure Ethernet TENA Signal
	 */

#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
	immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
	immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
	immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
	immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
#else
#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
#endif

#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
	/*
	 * Port C is used to control the PHY,MC68160.
	 */
	immr->im_ioport.iop_pcdir |=
			(PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);

	immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
	immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
	*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#endif /* MPC860ADS */

#if defined(CONFIG_AMX860)
	/*
	 * Port B is used to control the PHY,MC68160.
	 */
	immr->im_cpm.cp_pbdir |=
			(PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);

	immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
	immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);

	immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
	immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
#endif /* AMX860 */

#endif /* 0 */

#ifdef CONFIG_RPXCLASSIC
	*((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
	*((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
#endif

#ifdef CONFIG_RPXLITE
	*((uchar *) BCSR0) |= BCSR0_ETHEN;
#endif

#ifdef CONFIG_MBX
	board_ether_init ();
#endif

	/*
	 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
	 */

	immr->im_cpm.cp_scc[scc_index].scc_gsmrl |=
			(SCC_GSMRL_ENR | SCC_GSMRL_ENT);

	/*
	 * Work around transmit problem with first eth packet
	 */
#if defined (CONFIG_FADS)
	udelay (10000);				/* wait 10 ms */
#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
	udelay (100000);			/* wait 100 ms */
#endif
}

static void scc_halt (int scc_index)
{
	volatile immap_t *immr = (immap_t *) CFG_IMMR;

	immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
			~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
	immr->im_ioport.iop_pcso  &=  ~(PC_ENET_CLSN | PC_ENET_RENA);
}

static int scc_send (int index, volatile void *packet, int length)
{
	int i, j = 0;

	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
		udelay (1);		/* will also trigger Wd if needed */
		j++;
	}
	if (j >= TOUT_LOOP)
		printf ("TX not ready\n");
	rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
	rtx->txbd[txIdx].cbd_datlen = length;
	rtx->txbd[txIdx].cbd_sc |=
			(BD_ENET_TX_READY | BD_ENET_TX_LAST | BD_ENET_TX_WRAP);
	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
		udelay (1);		/* will also trigger Wd if needed */
		j++;
	}
	if (j >= TOUT_LOOP)
		printf ("TX timeout\n");
	i = (rtx->txbd[txIdx].
		 cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ;
	return i;
}

static int scc_recv (int index, void *packet, int max_length)
{
	int length = -1;

	if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
		goto Done;		/* nothing received */
	}

	if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) {
		length = rtx->rxbd[rxIdx].cbd_datlen - 4;
		memcpy (packet,
				(void *) (NetRxPackets[rxIdx]),
				length < max_length ? length : max_length);
	}

	/* Give the buffer back to the SCC. */
	rtx->rxbd[rxIdx].cbd_datlen = 0;

	/* wrap around buffer index when necessary */
	if ((rxIdx + 1) >= PKTBUFSRX) {
		rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
				(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
		rxIdx = 0;
	} else {
		rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
		rxIdx++;
	}

Done:
	return length;
}

  /*
   * Test routines
   */

static void packet_fill (char *packet, int length)
{
	char c = (char) length;
	int i;

	packet[0] = 0xFF;
	packet[1] = 0xFF;
	packet[2] = 0xFF;
	packet[3] = 0xFF;
	packet[4] = 0xFF;
	packet[5] = 0xFF;

	for (i = 6; i < length; i++) {
		packet[i] = c++;
	}
}

static int packet_check (char *packet, int length)
{
	char c = (char) length;
	int i;

	for (i = 6; i < length; i++) {
		if (packet[i] != c++)
			return -1;
	}

	return 0;
}

static int test_ctlr (int ctlr, int index)
{
	int res = -1;
	char packet_send[MAX_PACKET_LENGTH];
	char packet_recv[MAX_PACKET_LENGTH];
	int length;
	int i;
	int l;

	ctlr_proc[ctlr].init (index);

	for (i = 0; i < TEST_NUM; i++) {
		for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
			packet_fill (packet_send, l);

			ctlr_proc[ctlr].send (index, packet_send, l);

			length = ctlr_proc[ctlr].recv (index, packet_recv,
							MAX_PACKET_LENGTH);

			if (length != l || packet_check (packet_recv, length) < 0) {
				goto Done;
			}
		}
	}

	res = 0;

Done:

	ctlr_proc[ctlr].halt (index);

	/*
	 * SCC2 Ethernet parameter RAM space overlaps
	 * the SPI parameter RAM space. So we need to restore
	 * the SPI configuration after SCC2 ethernet test.
	 */
#if defined(CONFIG_SPI)
	if (ctlr == CTLR_SCC && index == 1) {
		spi_init_f ();
		spi_init_r ();
	}
#endif

	if (res != 0) {
		post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr],
				  index + 1);
	}

	return res;
}

int ether_post_test (int flags)
{
	int res = 0;
	int i;

	ctlr_proc[CTLR_SCC].init = scc_init;
	ctlr_proc[CTLR_SCC].halt = scc_halt;
	ctlr_proc[CTLR_SCC].send = scc_send;
	ctlr_proc[CTLR_SCC].recv = scc_recv;

	for (i = 0; i < CTRL_LIST_SIZE; i++) {
		if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
			res = -1;
		}
	}

#if !defined(CONFIG_8xx_CONS_NONE)
	serial_reinit_all ();
#endif
	return res;
}

#endif /* CONFIG_POST & CFG_POST_ETHER */

#endif /* CONFIG_POST */