sc520_cdp.c

嵌入式试验箱S3C2410的bootloader源代码

 * PAR11  ISAROM
 * PAR12  BOOTCS
 * PAR13  ROMCS1
 * PAR14  ROMCS2
 * PAR15  Port 0x680 LED display
 */

/*
 * This function should map a chunk of size bytes
 * of the system address space to the ISA bus
 *
 * The function will return the memory address
 * as seen by the host (which may very will be the
 * same as the bus address)
 */
u32 isa_map_rom(u32 bus_addr, int size)
{
	u32 par;

	PRINTF("isa_map_rom asked to map %d bytes at %x\n",
	       size, bus_addr);

	par = size;
	if (par < 0x80000) {
		par = 0x80000;
	}
	par >>= 12;
	par--;
	par&=0x7f;
	par <<= 18;
	par |= (bus_addr>>12);
	par |= 0x50000000;

	PRINTF ("setting PAR11 to %x\n", par);

	/* Map rom 0x10000 with PAR1 */
	write_mmcr_long(SC520_PAR11,  par);

	return bus_addr;
}

/*
 * this function removed any mapping created
 * with pci_get_rom_window()
 */
void isa_unmap_rom(u32 addr)
{
	PRINTF("isa_unmap_rom asked to unmap %x", addr);
	if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
		write_mmcr_long(SC520_PAR11, 0);
		PRINTF(" done\n");
		return;
	}
	PRINTF(" not ours\n");
}

#ifdef CONFIG_PCI
#define PCI_ROM_TEMP_SPACE 0x10000
/*
 * This function should map a chunk of size bytes
 * of the system address space to the PCI bus,
 * suitable to map PCI ROMS (bus address < 16M)
 * the function will return the host memory address
 * which should be converted into a bus address
 * before used to configure the PCI rom address
 * decoder
 */
u32 pci_get_rom_window(struct pci_controller *hose, int size)
{
	u32 par;

	par = size;
	if (par < 0x80000) {
		par = 0x80000;
	}
	par >>= 16;
	par--;
	par&=0x7ff;
	par <<= 14;
	par |= (PCI_ROM_TEMP_SPACE>>16);
	par |= 0x72000000;

	PRINTF ("setting PAR1 to %x\n", par);

	/* Map rom 0x10000 with PAR1 */
	write_mmcr_long(SC520_PAR1,  par);

	return PCI_ROM_TEMP_SPACE;
}

/*
 * this function removed any mapping created
 * with pci_get_rom_window()
 */
void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
{
	PRINTF("pci_remove_rom_window: %x", addr);
	if (addr == PCI_ROM_TEMP_SPACE) {
		write_mmcr_long(SC520_PAR1, 0);
		PRINTF(" done\n");
		return;
	}
	PRINTF(" not ours\n");

}

/*
 * This function is called in order to provide acces to the
 * legacy video I/O ports on the PCI bus.
 * After this function accesses to I/O ports 0x3b0-0x3bb and
 * 0x3c0-0x3df shuld result in transactions on the PCI bus.
 *
 */
int pci_enable_legacy_video_ports(struct pci_controller *hose)
{
	/* Map video memory to 0xa0000*/
	write_mmcr_long(SC520_PAR0,  0x7200400a);

	/* forward all I/O accesses to PCI */
	write_mmcr_byte(SC520_ADDDECCTL,
			read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);


	/* so we map away all io ports to pci (only way to access pci io
	 * below 0x400. But then we have to map back the portions that we dont
	 * use so that the generate cycles on the GPIO bus where the sio and
	 * ISA slots are connected, this requre the use of several PAR registers
	 */

	/* bring 0x100 - 0x1ef back to ISA using PAR5 */
	write_mmcr_long(SC520_PAR5, 0x30ef0100);

	/* IDE use 1f0-1f7 */

	/* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
	write_mmcr_long(SC520_PAR6, 0x30ff01f8);

	/* com2 use 2f8-2ff */

	/* bring 0x300 - 0x3af back to ISA using PAR7 */
	write_mmcr_long(SC520_PAR7, 0x30af0300);

	/* vga use 3b0-3bb */

	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
	write_mmcr_long(SC520_PAR8, 0x300303bc);

	/* vga use 3c0-3df */

	/* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
	write_mmcr_long(SC520_PAR9, 0x301503e0);

	/* ide use 3f6 */

	/* bring 0x3f7  back to ISA using PAR10 */
	write_mmcr_long(SC520_PAR10, 0x300003f7);

	/* com1 use 3f8-3ff */

	return 0;
}
#endif

/*
 * Miscelaneous platform dependent initialisations
 */

int board_init(void)
{
	init_sc520();
	bus_init();
	irq_init();

	/* max drive current on SDRAM */
	write_mmcr_word(SC520_DSCTL, 0x0100);

	/* enter debug mode after next reset (only if jumper is also set) */
	write_mmcr_byte(SC520_RESCFG, 0x08);
	/* configure the software timer to 33.333MHz */
	write_mmcr_byte(SC520_SWTMRCFG, 0);
	gd->bus_clk = 33333000;

	return 0;
}

int dram_init(void)
{
	init_sc520_dram();
	return 0;
}

void show_boot_progress(int val)
{
	outb(val&0xff, 0x80);
	outb((val&0xff00)>>8, 0x680);
}


int last_stage_init(void)
{
	int minor;
	int major;

	major = minor = 0;
	major |= ali512x_cio_in(23)?2:0;
	major |= ali512x_cio_in(22)?1:0;
	minor |= ali512x_cio_in(21)?2:0;
	minor |= ali512x_cio_in(20)?1:0;

	printf("AMD SC520 CDP revision %d.%d\n", major, minor);

	return 0;
}


void ssi_chip_select(int dev)
{

	/* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */
	switch (dev) {
	case 1: /* SPI EEPROM */
		ali512x_cio_out(16, 0);
		break;

	case 2: /* MW EEPROM */
		ali512x_cio_out(15, 1);
		break;

	case 3: /* AUX */
		ali512x_cio_out(14, 1);
		break;

	case 0:
		ali512x_cio_out(16, 1);
		ali512x_cio_out(15, 0);
		ali512x_cio_out(14, 0);
		break;

	default:
		printf("Illegal SSI device requested: %d\n", dev);
	}
}

void spi_eeprom_probe(int x)
{
}

int spi_eeprom_read(int x, int offset, char *buffer, int len)
{
       return 0;
}

int spi_eeprom_write(int x, int offset, char *buffer, int len)
{
       return 0;
}

void spi_init_f(void)
{
#ifdef CONFIG_SC520_CDP_USE_SPI
	spi_eeprom_probe(1);
#endif
#ifdef CONFIG_SC520_CDP_USE_MW
	mw_eeprom_probe(2);
#endif
}

ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
{
	int offset;
	int i;
	ssize_t res;

	offset = 0;
	for (i=0;i<alen;i++) {
		offset <<= 8;
		offset |= addr[i];
	}

#ifdef CONFIG_SC520_CDP_USE_SPI
	res = spi_eeprom_read(1, offset, buffer, len);
#endif
#ifdef CONFIG_SC520_CDP_USE_MW
	res = mw_eeprom_read(2, offset, buffer, len);
#endif
#if !defined(CONFIG_SC520_CDP_USE_SPI) && !defined(CONFIG_SC520_CDP_USE_MW)
	res = 0;
#endif
	return res;
}

ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
{
	int offset;
	int i;
	ssize_t res;

	offset = 0;
	for (i=0;i<alen;i++) {
		offset <<= 8;
		offset |= addr[i];
	}

#ifdef CONFIG_SC520_CDP_USE_SPI
	res = spi_eeprom_write(1, offset, buffer, len);
#endif
#ifdef CONFIG_SC520_CDP_USE_MW
	res = mw_eeprom_write(2, offset, buffer, len);
#endif
#if !defined(CONFIG_SC520_CDP_USE_SPI) && !defined(CONFIG_SC520_CDP_USE_MW)
	res = 0;
#endif
	return res;
}