s3c24x0.h

嵌入式试验箱S3C2410的bootloader源代码

#endif
} /*__attribute__((__packed__))*/ S3C24X0_I2S;


/* I/O PORT (see manual chapter 9) */
typedef struct {
#ifdef CONFIG_S3C2400
    S3C24X0_REG32   PACON;
    S3C24X0_REG32   PADAT;

    S3C24X0_REG32   PBCON;
    S3C24X0_REG32   PBDAT;
    S3C24X0_REG32   PBUP;

    S3C24X0_REG32   PCCON;
    S3C24X0_REG32   PCDAT;
    S3C24X0_REG32   PCUP;

    S3C24X0_REG32   PDCON;
    S3C24X0_REG32   PDDAT;
    S3C24X0_REG32   PDUP;

    S3C24X0_REG32   PECON;
    S3C24X0_REG32   PEDAT;
    S3C24X0_REG32   PEUP;

    S3C24X0_REG32   PFCON;
    S3C24X0_REG32   PFDAT;
    S3C24X0_REG32   PFUP;

    S3C24X0_REG32   PGCON;
    S3C24X0_REG32   PGDAT;
    S3C24X0_REG32   PGUP;

    S3C24X0_REG32   OPENCR;

    S3C24X0_REG32   MISCCR;
    S3C24X0_REG32   EXTINT;
#endif
#ifdef CONFIG_S3C2410
    S3C24X0_REG32   GPACON;
    S3C24X0_REG32   GPADAT;
    S3C24X0_REG32   res1[2];
    S3C24X0_REG32   GPBCON;
    S3C24X0_REG32   GPBDAT;
    S3C24X0_REG32   GPBUP;
    S3C24X0_REG32   res2;
    S3C24X0_REG32   GPCCON;
    S3C24X0_REG32   GPCDAT;
    S3C24X0_REG32   GPCUP;
    S3C24X0_REG32   res3;
    S3C24X0_REG32   GPDCON;
    S3C24X0_REG32   GPDDAT;
    S3C24X0_REG32   GPDUP;
    S3C24X0_REG32   res4;
    S3C24X0_REG32   GPECON;
    S3C24X0_REG32   GPEDAT;
    S3C24X0_REG32   GPEUP;
    S3C24X0_REG32   res5;
    S3C24X0_REG32   GPFCON;
    S3C24X0_REG32   GPFDAT;
    S3C24X0_REG32   GPFUP;
    S3C24X0_REG32   res6;
    S3C24X0_REG32   GPGCON;
    S3C24X0_REG32   GPGDAT;
    S3C24X0_REG32   GPGUP;
    S3C24X0_REG32   res7;
    S3C24X0_REG32   GPHCON;
    S3C24X0_REG32   GPHDAT;
    S3C24X0_REG32   GPHUP;
    S3C24X0_REG32   res8;

    S3C24X0_REG32   MISCCR;
    S3C24X0_REG32   DCLKCON;
    S3C24X0_REG32   EXTINT0;
    S3C24X0_REG32   EXTINT1;
    S3C24X0_REG32   EXTINT2;
    S3C24X0_REG32   EINTFLT0;
    S3C24X0_REG32   EINTFLT1;
    S3C24X0_REG32   EINTFLT2;
    S3C24X0_REG32   EINTFLT3;
    S3C24X0_REG32   EINTMASK;
    S3C24X0_REG32   EINTPEND;
    S3C24X0_REG32   GSTATUS0;
    S3C24X0_REG32   GSTATUS1;
    S3C24X0_REG32   GSTATUS2;
    S3C24X0_REG32   GSTATUS3;
    S3C24X0_REG32   GSTATUS4;

    /* s3c2440 */
    S3C24X0_REG32   res9[4];
    S3C24X0_REG32   GPJCON;
    S3C24X0_REG32   GPJDAT;
    S3C24X0_REG32   GPJUP;
#endif
} /*__attribute__((__packed__))*/ S3C24X0_GPIO;


/* RTC (see manual chapter 17) */
typedef struct {
#ifdef __BIG_ENDIAN
    S3C24X0_REG8    res1[67];
    S3C24X0_REG8    RTCCON;
    S3C24X0_REG8    res2[3];
    S3C24X0_REG8    TICNT;
    S3C24X0_REG8    res3[11];
    S3C24X0_REG8    RTCALM;
    S3C24X0_REG8    res4[3];
    S3C24X0_REG8    ALMSEC;
    S3C24X0_REG8    res5[3];
    S3C24X0_REG8    ALMMIN;
    S3C24X0_REG8    res6[3];
    S3C24X0_REG8    ALMHOUR;
    S3C24X0_REG8    res7[3];
    S3C24X0_REG8    ALMDATE;
    S3C24X0_REG8    res8[3];
    S3C24X0_REG8    ALMMON;
    S3C24X0_REG8    res9[3];
    S3C24X0_REG8    ALMYEAR;
    S3C24X0_REG8    res10[3];
    S3C24X0_REG8    RTCRST;
    S3C24X0_REG8    res11[3];
    S3C24X0_REG8    BCDSEC;
    S3C24X0_REG8    res12[3];
    S3C24X0_REG8    BCDMIN;
    S3C24X0_REG8    res13[3];
    S3C24X0_REG8    BCDHOUR;
    S3C24X0_REG8    res14[3];
    S3C24X0_REG8    BCDDATE;
    S3C24X0_REG8    res15[3];
    S3C24X0_REG8    BCDDAY;
    S3C24X0_REG8    res16[3];
    S3C24X0_REG8    BCDMON;
    S3C24X0_REG8    res17[3];
    S3C24X0_REG8    BCDYEAR;
#else /*  little endian */
    S3C24X0_REG8    res0[64];
    S3C24X0_REG8    RTCCON;
    S3C24X0_REG8    res1[3];
    S3C24X0_REG8    TICNT;
    S3C24X0_REG8    res2[11];
    S3C24X0_REG8    RTCALM;
    S3C24X0_REG8    res3[3];
    S3C24X0_REG8    ALMSEC;
    S3C24X0_REG8    res4[3];
    S3C24X0_REG8    ALMMIN;
    S3C24X0_REG8    res5[3];
    S3C24X0_REG8    ALMHOUR;
    S3C24X0_REG8    res6[3];
    S3C24X0_REG8    ALMDATE;
    S3C24X0_REG8    res7[3];
    S3C24X0_REG8    ALMMON;
    S3C24X0_REG8    res8[3];
    S3C24X0_REG8    ALMYEAR;
    S3C24X0_REG8    res9[3];
    S3C24X0_REG8    RTCRST;
    S3C24X0_REG8    res10[3];
    S3C24X0_REG8    BCDSEC;
    S3C24X0_REG8    res11[3];
    S3C24X0_REG8    BCDMIN;
    S3C24X0_REG8    res12[3];
    S3C24X0_REG8    BCDHOUR;
    S3C24X0_REG8    res13[3];
    S3C24X0_REG8    BCDDATE;
    S3C24X0_REG8    res14[3];
    S3C24X0_REG8    BCDDAY;
    S3C24X0_REG8    res15[3];
    S3C24X0_REG8    BCDMON;
    S3C24X0_REG8    res16[3];
    S3C24X0_REG8    BCDYEAR;
    S3C24X0_REG8    res17[3];
#endif
} /*__attribute__((__packed__))*/ S3C24X0_RTC;


/* ADC (see manual chapter 16) */
typedef struct {
    S3C24X0_REG32   ADCCON;
    S3C24X0_REG32   ADCDAT;
} /*__attribute__((__packed__))*/ S3C2400_ADC;


/* ADC (see manual chapter 16) */
typedef struct {
    S3C24X0_REG32   ADCCON;
    S3C24X0_REG32   ADCTSC;
    S3C24X0_REG32   ADCDLY;
    S3C24X0_REG32   ADCDAT0;
    S3C24X0_REG32   ADCDAT1;
} /*__attribute__((__packed__))*/ S3C2410_ADC;


/* SPI (see manual chapter 22) */
typedef struct {
    S3C24X0_REG32   SPCON;
    S3C24X0_REG32   SPSTA;
    S3C24X0_REG32   SPPIN;
    S3C24X0_REG32   SPPRE;
    S3C24X0_REG32   SPTDAT;
    S3C24X0_REG32   SPRDAT;
    S3C24X0_REG32   res[2];
} __attribute__((__packed__)) S3C24X0_SPI_CHANNEL;

typedef struct {
    S3C24X0_SPI_CHANNEL ch[S3C24X0_SPI_CHANNELS];
} /*__attribute__((__packed__))*/ S3C24X0_SPI;


/* MMC INTERFACE (see S3C2400 manual chapter 19) */
typedef struct {
#ifdef __BIG_ENDIAN
    S3C24X0_REG8    res1[3];
    S3C24X0_REG8    MMCON;
    S3C24X0_REG8    res2[3];
    S3C24X0_REG8    MMCRR;
    S3C24X0_REG8    res3[3];
    S3C24X0_REG8    MMFCON;
    S3C24X0_REG8    res4[3];
    S3C24X0_REG8    MMSTA;
    S3C24X0_REG16   res5;
    S3C24X0_REG16   MMFSTA;
    S3C24X0_REG8    res6[3];
    S3C24X0_REG8    MMPRE;
    S3C24X0_REG16   res7;
    S3C24X0_REG16   MMLEN;
    S3C24X0_REG8    res8[3];
    S3C24X0_REG8    MMCR7;
    S3C24X0_REG32   MMRSP[4];
    S3C24X0_REG8    res9[3];
    S3C24X0_REG8    MMCMD0;
    S3C24X0_REG32   MMCMD1;
    S3C24X0_REG16   res10;
    S3C24X0_REG16   MMCR16;
    S3C24X0_REG8    res11[3];
    S3C24X0_REG8    MMDAT;
#else
    S3C24X0_REG8    MMCON;
    S3C24X0_REG8    res1[3];
    S3C24X0_REG8    MMCRR;
    S3C24X0_REG8    res2[3];
    S3C24X0_REG8    MMFCON;
    S3C24X0_REG8    res3[3];
    S3C24X0_REG8    MMSTA;
    S3C24X0_REG8    res4[3];
    S3C24X0_REG16   MMFSTA;
    S3C24X0_REG16   res5;
    S3C24X0_REG8    MMPRE;
    S3C24X0_REG8    res6[3];
    S3C24X0_REG16   MMLEN;
    S3C24X0_REG16   res7;
    S3C24X0_REG8    MMCR7;
    S3C24X0_REG8    res8[3];
    S3C24X0_REG32   MMRSP[4];
    S3C24X0_REG8    MMCMD0;
    S3C24X0_REG8    res9[3];
    S3C24X0_REG32   MMCMD1;
    S3C24X0_REG16   MMCR16;
    S3C24X0_REG16   res10;
    S3C24X0_REG8    MMDAT;
    S3C24X0_REG8    res11[3];
#endif
} /*__attribute__((__packed__))*/ S3C2400_MMC;


/* SD INTERFACE (see S3C2410 manual chapter 19) */
typedef struct {
    S3C24X0_REG32   SDICON;
    S3C24X0_REG32   SDIPRE;
    S3C24X0_REG32   SDICARG;
    S3C24X0_REG32   SDICCON;
    S3C24X0_REG32   SDICSTA;
    S3C24X0_REG32   SDIRSP0;
    S3C24X0_REG32   SDIRSP1;
    S3C24X0_REG32   SDIRSP2;
    S3C24X0_REG32   SDIRSP3;
    S3C24X0_REG32   SDIDTIMER;
    S3C24X0_REG32   SDIBSIZE;
    S3C24X0_REG32   SDIDCON;
    S3C24X0_REG32   SDIDCNT;
    S3C24X0_REG32   SDIDSTA;
    S3C24X0_REG32   SDIFSTA;
#ifdef __BIG_ENDIAN
    S3C24X0_REG8    res[3];
    S3C24X0_REG8    SDIDAT;
#else
    S3C24X0_REG8    SDIDAT;
    S3C24X0_REG8    res[3];
#endif
    S3C24X0_REG32   SDIIMSK;
} /*__attribute__((__packed__))*/ S3C2410_SDI;


#if 0
/* Memory control */
#define rBWSCON         (*(volatile unsigned *)0x48000000)
#define rBANKCON0       (*(volatile unsigned *)0x48000004)
#define rBANKCON1       (*(volatile unsigned *)0x48000008)
#define rBANKCON2       (*(volatile unsigned *)0x4800000C)
#define rBANKCON3       (*(volatile unsigned *)0x48000010)
#define rBANKCON4       (*(volatile unsigned *)0x48000014)
#define rBANKCON5       (*(volatile unsigned *)0x48000018)
#define rBANKCON6       (*(volatile unsigned *)0x4800001C)
#define rBANKCON7       (*(volatile unsigned *)0x48000020)
#define rREFRESH        (*(volatile unsigned *)0x48000024)
#define rBANKSIZE       (*(volatile unsigned *)0x48000028)
#define rMRSRB6         (*(volatile unsigned *)0x4800002C)
#define rMRSRB7         (*(volatile unsigned *)0x48000030)


/* USB HOST */
#define rHcRevision     (*(volatile unsigned *)0x49000000)
#define rHcControl      (*(volatile unsigned *)0x49000004)
#define rHcCommonStatus     (*(volatile unsigned *)0x49000008)
#define rHcInterruptStatus  (*(volatile unsigned *)0x4900000C)
#define rHcInterruptEnable  (*(volatile unsigned *)0x49000010)
#define rHcInterruptDisable (*(volatile unsigned *)0x49000014)
#define rHcHCCA         (*(volatile unsigned *)0x49000018)
#define rHcPeriodCuttendED  (*(volatile unsigned *)0x4900001C)
#define rHcControlHeadED    (*(volatile unsigned *)0x49000020)
#define rHcControlCurrentED (*(volatile unsigned *)0x49000024)
#define rHcBulkHeadED       (*(volatile unsigned *)0x49000028)
#define rHcBuldCurrentED    (*(volatile unsigned *)0x4900002C)
#define rHcDoneHead     (*(volatile unsigned *)0x49000030)
#define rHcRmInterval       (*(volatile unsigned *)0x49000034)
#define rHcFmRemaining      (*(volatile unsigned *)0x49000038)
#define rHcFmNumber     (*(volatile unsigned *)0x4900003C)
#define rHcPeriodicStart    (*(volatile unsigned *)0x49000040)
#define rHcLSThreshold      (*(volatile unsigned *)0x49000044)
#define rHcRhDescriptorA    (*(volatile unsigned *)0x49000048)
#define rHcRhDescriptorB    (*(volatile unsigned *)0x4900004C)
#define rHcRhStatus     (*(volatile unsigned *)0x49000050)
#define rHcRhPortStatus1    (*(volatile unsigned *)0x49000054)
#define rHcRhPortStatus2    (*(volatile unsigned *)0x49000058)


/* INTERRUPT */
#define rSRCPND         (*(volatile unsigned *)0x4A000000)
#define rINTMOD         (*(volatile unsigned *)0x4A000004)
#define rINTMSK         (*(volatile unsigned *)0x4A000008)
#define rPRIORITY       (*(volatile unsigned *)0x4A00000C)
#define rINTPND         (*(volatile unsigned *)0x4A000010)
#define rINTOFFSET      (*(volatile unsigned *)0x4A000014)
#define rSUBSRCPND      (*(volatile unsigned *)0x4A000018)
#define rINTSUBMSK      (*(volatile unsigned *)0x4A00001C)


/* DMA */
#define rDISRC0         (*(volatile unsigned *)0x4B000000)
#define rDISRCC0        (*(volatile unsigned *)0x4B000004)
#define rDIDST0         (*(volatile unsigned *)0x4B000008)
#define rDIDSTC0        (*(volatile unsigned *)0x4B00000C)
#define rDCON0          (*(volatile unsigned *)0x4B000010)
#define rDSTAT0         (*(volatile unsigned *)0x4B000014)
#define rDCSRC0         (*(volatile unsigned *)0x4B000018)
#define rDCDST0         (*(volatile unsigned *)0x4B00001C)
#define rDMASKTRIG0     (*(volatile unsigned *)0x4B000020)
#define rDISRC1         (*(volatile unsigned *)0x4B000040)
#define rDISRCC1        (*(volatile unsigned *)0x4B000044)
#define rDIDST1         (*(volatile unsigned *)0x4B000048)
#define rDIDSTC1        (*(volatile unsigned *)0x4B00004C)
#define rDCON1          (*(volatile unsigned *)0x4B000050)
#define rDSTAT1         (*(volatile unsigned *)0x4B000054)
#define rDCSRC1         (*(volatile unsigned *)0x4B000058)
#define rDCDST1         (*(volatile unsigned *)0x4B00005C)
#define rDMASKTRIG1     (*(volatile unsigned *)0x4B000060)
#define rDISRC2         (*(volatile unsigned *)0x4B000080)
#define rDISRCC2        (*(volatile unsigned *)0x4B000084)
#define rDIDST2         (*(volatile unsigned *)0x4B000088)
#define rDIDSTC2        (*(volatile unsigned *)0x4B00008C)
#define rDCON2          (*(volatile unsigned *)0x4B000090)
#define rDSTAT2         (*(volatile unsigned *)0x4B000094)
#define rDCSRC2         (*(volatile unsigned *)0x4B000098)
#define rDCDST2         (*(volatile unsigned *)0x4B00009C)
#define rDMASKTRIG2     (*(volatile unsigned *)0x4B0000A0)
#define rDISRC3         (*(volatile unsigned *)0x4B0000C0)
#define rDISRCC3        (*(volatile unsigned *)0x4B0000C4)
#define rDIDST3         (*(volatile unsigned *)0x4B0000C8)
#define rDIDSTC3        (*(volatile unsigned *)0x4B0000CC)
#define rDCON3          (*(volatile unsigned *)0x4B0000D0)
#define rDSTAT3         (*(volatile unsigned *)0x4B0000D4)
#define rDCSRC3         (*(volatile unsigned *)0x4B0000D8)
#define rDCDST3         (*(volatile unsigned *)0x4B0000DC)
#define rDMASKTRIG3     (*(volatile unsigned *)0x4B0000E0)


/* CLOCK & POWER MANAGEMENT */
#define rLOCKTIME       (*(volatile unsigned *)0x4C000000)
#define rMPLLCON        (*(volatile unsigned *)0x4C000004)
#define rUPLLCON        (*(volatile unsigned *)0x4C000008)
#define rCLKCON         (*(volatile unsigned *)0x4C00000C)