cpc45.h

嵌入式试验箱S3C2410的bootloader源代码

#define CFG_BANK3_ENABLE	0
#define CFG_BANK4_START		0x3ff00000
#define CFG_BANK4_END		0x3fffffff
#define CFG_BANK4_ENABLE	0
#define CFG_BANK5_START		0x3ff00000
#define CFG_BANK5_END		0x3fffffff
#define CFG_BANK5_ENABLE	0
#define CFG_BANK6_START		0x3ff00000
#define CFG_BANK6_END		0x3fffffff
#define CFG_BANK6_ENABLE	0
#define CFG_BANK7_START		0x3ff00000
#define CFG_BANK7_END		0x3fffffff
#define CFG_BANK7_ENABLE	0

#define CFG_ODCR		0xff
#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
					/* currently accessed page in memory	*/
					/* see 8240 book for details		*/

#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)

#define CFG_DBAT0L  CFG_IBAT0L
#define CFG_DBAT0U  CFG_IBAT0U
#define CFG_DBAT1L  CFG_IBAT1L
#define CFG_DBAT1U  CFG_IBAT1U
#define CFG_DBAT2L  CFG_IBAT2L
#define CFG_DBAT2U  CFG_IBAT2U
#define CFG_DBAT3L  CFG_IBAT3L
#define CFG_DBAT3U  CFG_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
#define CFG_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
#define INTEL_ID_28F160F3T	0x88F388F3	/*  16M = 1M x 16 top boot sector	*/
#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

	/* Warining: environment is not EMBEDDED in the ppcboot code.
	 * It's stored in flash separately.
	 */
#define CFG_ENV_IS_IN_FLASH	    1

#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x7F8000)
#define CFG_ENV_SIZE		0x4000	/* Size of the Environment		*/
#define CFG_ENV_OFFSET		0	/* starting right at the beginning	*/
#define CFG_ENV_SECT_SIZE	0x8000 /* Size of the Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/


#define SRAM_BASE		0x80000000	/* SRAM base address	*/
#define SRAM_END		0x801FFFFF

/*----------------------------------------------------------------------*/
/* CPC45 Memory Map							*/
/*----------------------------------------------------------------------*/
#define SRAM_BASE	0x80000000	/* SRAM base address		*/
#define ST16552_A_BASE	0x80200000	/* ST16552 channel A		*/
#define ST16552_B_BASE	0x80400000	/* ST16552 channel A		*/
#define BCSR_BASE	0x80600000	/* board control / status registers */
#define DISPLAY_BASE	0x80600040	/* DISPLAY base			*/
#define PCMCIA_MEM_BASE 0x83000000	/* PCMCIA memory window base	*/
#define PCMCIA_IO_BASE	0xFE000000	/* PCMCIA IO window base	*/


/*---------------------------------------------------------------------*/
/* CPC45 Control/Status Registers				       */
/*---------------------------------------------------------------------*/
#define IRQ_ENA_1		*((volatile uchar*)(BCSR_BASE + 0x00))
#define IRQ_STAT_1		*((volatile uchar*)(BCSR_BASE + 0x01))
#define IRQ_ENA_2		*((volatile uchar*)(BCSR_BASE + 0x02))
#define IRQ_STAT_2		*((volatile uchar*)(BCSR_BASE + 0x03))
#define BOARD_CTRL		*((volatile uchar*)(BCSR_BASE + 0x04))
#define BOARD_STAT		*((volatile uchar*)(BCSR_BASE + 0x05))
#define WDG_START		*((volatile uchar*)(BCSR_BASE + 0x06))
#define WDG_PRESTOP		*((volatile uchar*)(BCSR_BASE + 0x06))
#define WDG_STOP		*((volatile uchar*)(BCSR_BASE + 0x06))
#define BOARD_REV		*((volatile uchar*)(BCSR_BASE + 0x07))

/* IRQ_ENA_1 bit definitions */
#define I_ENA_1_IERA	0x80		/* INTA enable			*/
#define I_ENA_1_IERB	0x40		/* INTB enable			*/
#define I_ENA_1_IERC	0x20		/* INTC enable			*/
#define I_ENA_1_IERD	0x10		/* INTD enable			*/

/* IRQ_STAT_1 bit definitions */
#define I_STAT_1_INTA	0x80		/* INTA status			*/
#define I_STAT_1_INTB	0x40		/* INTB status			*/
#define I_STAT_1_INTC	0x20		/* INTC status			*/
#define I_STAT_1_INTD	0x10		/* INTD status			*/

/* IRQ_ENA_2 bit definitions */
#define I_ENA_2_IEAB	0x80		/* ABORT IRQ enable		*/
#define I_ENA_2_IEK1	0x40		/* KEY1 IRQ enable		*/
#define I_ENA_2_IEK2	0x20		/* KEY2 IRQ enable		*/
#define I_ENA_2_IERT	0x10		/* RTC IRQ enable		*/
#define I_ENA_2_IESM	0x08		/* LM81 IRQ enable		*/
#define I_ENA_2_IEDG	0x04		/* DEGENERATING IRQ enable	*/
#define I_ENA_2_IES2	0x02		/* ST16552/B IRQ enable		*/
#define I_ENA_2_IES1	0x01		/* ST16552/A IRQ enable		*/

/* IRQ_STAT_2 bit definitions */
#define I_STAT_2_ABO	0x80		/* ABORT IRQ status		*/
#define I_STAT_2_KY1	0x40		/* KEY1 IRQ status		*/
#define I_STAT_2_KY2	0x20		/* KEY2 IRQ status		*/
#define I_STAT_2_RTC	0x10		/* RTC IRQ status		*/
#define I_STAT_2_SMN	0x08		/* LM81 IRQ status		*/
#define I_STAT_2_DEG	0x04		/* DEGENERATING IRQ status	*/
#define I_STAT_2_SIO2	0x02		/* ST16552/B IRQ status		*/
#define I_STAT_2_SIO1	0x01		/* ST16552/A IRQ status		*/

/* BOARD_CTRL bit definitions */
#define USER_LEDS		2			/* 2 user LEDs	*/

#if (USER_LEDS == 4)
#define B_CTRL_WRSE		0x80
#define B_CTRL_KRSE		0x40
#define B_CTRL_FWRE		0x20		/* Flash write enable		*/
#define B_CTRL_FWPT		0x10		/* Flash write protect		*/
#define B_CTRL_LED3		0x08		/* LED 3 control		*/
#define B_CTRL_LED2		0x04		/* LED 2 control		*/
#define B_CTRL_LED1		0x02		/* LED 1 control		*/
#define B_CTRL_LED0		0x01		/* LED 0 control		*/
#else
#define B_CTRL_WRSE		0x80
#define B_CTRL_KRSE		0x40
#define B_CTRL_FWRE_1		0x20		/* Flash write enable		*/
#define B_CTRL_FWPT_1		0x10		/* Flash write protect		*/
#define B_CTRL_LED1		0x08		/* LED 1 control		*/
#define B_CTRL_LED0		0x04		/* LED 0 control		*/
#define B_CTRL_FWRE_0		0x02		/* Flash write enable		*/
#define B_CTRL_FWPT_0		0x01		/* Flash write protect		*/
#endif

/* BOARD_STAT bit definitions */
#define B_STAT_WDGE		0x80
#define B_STAT_WDGS		0x40
#define B_STAT_WRST		0x20
#define B_STAT_KRST		0x10
#define B_STAT_CSW3		0x08		/* sitch bit 3 status		*/
#define B_STAT_CSW2		0x04		/* sitch bit 2 status		*/
#define B_STAT_CSW1		0x02		/* sitch bit 1 status		*/
#define B_STAT_CSW0		0x01		/* sitch bit 0 status		*/

/*---------------------------------------------------------------------*/
/* Display addresses						       */
/*---------------------------------------------------------------------*/
#define DISP_UDC_RAM	(DISPLAY_BASE + 0x08)	/* UDC RAM	       */
#define DISP_CHR_RAM	(DISPLAY_BASE + 0x18)	/* character Ram       */
#define DISP_FLASH	(DISPLAY_BASE + 0x20)	/* Flash Ram	       */

#define DISP_UDC_ADR	*((volatile uchar*)(DISPLAY_BASE + 0x00))	/* UDC Address Reg.    */
#define DISP_CWORD	*((volatile uchar*)(DISPLAY_BASE + 0x10))	/* Control Word Reg.   */

#define DISP_DIG0	*((volatile uchar*)(DISP_CHR_RAM + 0x00))	/* Digit 0 address     */
#define DISP_DIG1	*((volatile uchar*)(DISP_CHR_RAM + 0x01))	/* Digit 0 address     */
#define DISP_DIG2	*((volatile uchar*)(DISP_CHR_RAM + 0x02))	/* Digit 0 address     */
#define DISP_DIG3	*((volatile uchar*)(DISP_CHR_RAM + 0x03))	/* Digit 0 address     */
#define DISP_DIG4	*((volatile uchar*)(DISP_CHR_RAM + 0x04))	/* Digit 0 address     */
#define DISP_DIG5	*((volatile uchar*)(DISP_CHR_RAM + 0x05))	/* Digit 0 address     */
#define DISP_DIG6	*((volatile uchar*)(DISP_CHR_RAM + 0x06))	/* Digit 0 address     */
#define DISP_DIG7	*((volatile uchar*)(DISP_CHR_RAM + 0x07))	/* Digit 0 address     */


/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI			/* include pci support			*/
#undef	CONFIG_PCI_PNP
#undef	CONFIG_PCI_SCAN_SHOW

#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/

#define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/

#define PCI_ENET0_IOADDR	0x82000000
#define PCI_ENET0_MEMADDR	0x82000000
#define PCI_PLX9030_IOADDR	0x82100000
#define PCI_PLX9030_MEMADDR	0x82100000

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 */

#define CONFIG_I82365

#define CFG_PCMCIA_MEM_ADDR	PCMCIA_MEM_BASE
#define CFG_PCMCIA_MEM_SIZE	0x1000

#define CONFIG_PCMCIA_SLOT_A

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for IDE not supported	*/
#define	CONFIG_IDE_LED			/* LED   for IDE is  supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR

#define CFG_ATA_DATA_OFFSET	CFG_PCMCIA_MEM_SIZE

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x400)

#define CONFIG_DOS_PARTITION

#endif	/* __CONFIG_H */