📄 omap1510.h
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#define OMAP_DMA_BASE OMAP1510_DMA_BASE/* Global Register selection */#define NO_GLOBAL_DMA_ACCESS 0/* Channel select field * NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc... */#define LCD_CHANNEL 0xc/* Register Select Field (LCD) */#define DMA_LCD_CTRL 0#define DMA_LCD_TOP_F1_L 1#define DMA_LCD_TOP_F1_U 2#define DMA_LCD_BOT_F1_L 3#define DMA_LCD_BOT_F1_U 4#define LCD_FRAME_MODE (1<<0)#define LCD_FRAME_IT_IE (1<<1)#define LCD_BUS_ERROR_IT_IE (1<<2)#define LCD_FRAME_1_IT_COND (1<<3)#define LCD_FRAME_2_IT_COND (1<<4)#define LCD_BUS_ERROR_IT_COND (1<<5)#define LCD_SOURCE_IMIF (1<<6)/* * Real-Time Clock */#define RTC_SECONDS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x00)#define RTC_MINUTES (volatile __u8 *)(OMAP1510_RTC_BASE + 0x04)#define RTC_HOURS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x08)#define RTC_DAYS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C)#define RTC_MONTHS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x10)#define RTC_YEARS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x14)#define RTC_CTRL (volatile __u8 *)(OMAP1510_RTC_BASE + 0x40)/* --------------------------------------------------------------------------- * OMAP1510 Interrupt Handlers * --------------------------------------------------------------------------- * */#define OMAP_IH1_BASE 0xfffecb00#define OMAP_IH2_BASE 0xfffe0000#define OMAP1510_ITR 0x0#define OMAP1510_MASK 0x4#define INTERRUPT_HANDLER_BASE OMAP_IH1_BASE#define INTERRUPT_INPUT_REGISTER OMAP1510_ITR#define INTERRUPT_MASK_REGISTER OMAP1510_MASK/* --------------------------------------------------------------------------- * OMAP1510 TIMERS * --------------------------------------------------------------------------- * */#define OMAP1510_32kHz_TIMER_BASE 0xfffb9000/* 32k Timer Registers */#define TIMER32k_CR 0x08#define TIMER32k_TVR 0x00#define TIMER32k_TCR 0x04/* 32k Timer Control Register definition */#define TIMER32k_TSS (1<<0)#define TIMER32k_TRB (1<<1)#define TIMER32k_INT (1<<2)#define TIMER32k_ARL (1<<3)/* MPU Timer base addresses */#define OMAP1510_MPUTIMER_BASE 0xfffec500#define OMAP1510_MPUTIMER_OFF 0x00000100#define OMAP1510_TIMER1_BASE 0xfffec500#define OMAP1510_TIMER2_BASE 0xfffec600#define OMAP1510_TIMER3_BASE 0xfffec700/* MPU Timer Registers */#define CNTL_TIMER 0#define LOAD_TIM 4#define READ_TIM 8/* CNTL_TIMER register bits */#define MPUTIM_FREE (1<<6)#define MPUTIM_CLOCK_ENABLE (1<<5)#define MPUTIM_PTV_MASK (0x7<<PTV_BIT)#define MPUTIM_PTV_BIT 2#define MPUTIM_AR (1<<1)#define MPUTIM_ST (1<<0)/* --------------------------------------------------------------------------- * OMAP1510 GPIO (SHARED) * --------------------------------------------------------------------------- * */#define GPIO_DATA_INPUT_REG (OMAP1510_GPIO_BASE + 0x0)#define GPIO_DATA_OUTPUT_REG (OMAP1510_GPIO_BASE + 0x4)#define GPIO_DIR_CONTROL_REG (OMAP1510_GPIO_BASE + 0x8)#define GPIO_INT_CONTROL_REG (OMAP1510_GPIO_BASE + 0xc)#define GPIO_INT_MASK_REG (OMAP1510_GPIO_BASE + 0x10)#define GPIO_INT_STATUS_REG (OMAP1510_GPIO_BASE + 0x14)#define GPIO_PIN_CONTROL_REG (OMAP1510_GPIO_BASE + 0x18)/* --------------------------- * OMAP1510 MPUIO (ARM only) *---------------------------- */#define OMAP1510_MPUIO_BASE 0xFFFB5000#define MPUIO_DATA_INPUT_REG (OMAP1510_MPUIO_BASE + 0x0)#define MPUIO_DATA_OUTPUT_REG (OMAP1510_MPUIO_BASE + 0x4)#define MPUIO_DIR_CONTROL_REG (OMAP1510_MPUIO_BASE + 0x8)/* --------------------------------------------------------------------------- * OMAP1510 TIPB (only) * --------------------------------------------------------------------------- * */#define TIPB_PUBLIC_CNTL_BASE 0xfffed300#define MPU_PUBLIC_TIPB_CNTL_REG (TIPB_PUBLIC_CNTL_BASE + 0x8)#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00#define MPU_PRIVATE_TIPB_CNTL_REG (TIPB_PRIVATE_CNTL_BASE + 0x8)/* * --------------------------------------------------------------------------- * OMAP1510 Camera Interface * --------------------------------------------------------------------------- */#define CAMERA_BASE (IO_BASE + 0x6800)#define CAM_CTRLCLOCK_REG (CAMERA_BASE + 0x00)#define CAM_IT_STATUS_REG (CAMERA_BASE + 0x04)#define CAM_MODE_REG (CAMERA_BASE + 0x08)#define CAM_STATUS_REG (CAMERA_BASE + 0x0C)#define CAM_CAMDATA_REG (CAMERA_BASE + 0x10)#define CAM_GPIO_REG (CAMERA_BASE + 0x14)#define CAM_PEAK_CTR_REG (CAMERA_BASE + 0x18)#if 0#ifndef __ASSEMBLY__typedef struct { __u32 ctrlclock; __u32 it_status; __u32 mode; __u32 status; __u32 camdata; __u32 gpio; __u32 peak_counter;} camera_regs_t;#endif#endif/* CTRLCLOCK bit shifts */#define FOSCMOD_BIT 0#define FOSCMOD_MASK (0x7 << FOSCMOD_BIT)#define FOSCMOD_12MHz 0x0#define FOSCMOD_6MHz 0x2#define FOSCMOD_9_6MHz 0x4#define FOSCMOD_24MHz 0x5#define FOSCMOD_8MHz 0x6#define POLCLK (1<<3)#define CAMEXCLK_EN (1<<4)#define MCLK_EN (1<<5)#define DPLL_EN (1<<6)#define LCLK_EN (1<<7)/* IT_STATUS bit shifts */#define V_UP (1<<0)#define V_DOWN (1<<1)#define H_UP (1<<2)#define H_DOWN (1<<3)#define FIFO_FULL (1<<4)#define DATA_XFER (1<<5)/* MODE bit shifts */#define CAMOSC (1<<0)#define IMGSIZE_BIT 1#define IMGSIZE_MASK (0x3 << IMGSIZE_BIT)#define IMGSIZE_CIF (0x0 << IMGSIZE_BIT) /* 352x288 */#define IMGSIZE_QCIF (0x1 << IMGSIZE_BIT) /* 176x144 */#define IMGSIZE_VGA (0x2 << IMGSIZE_BIT) /* 640x480 */#define IMGSIZE_QVGA (0x3 << IMGSIZE_BIT) /* 320x240 */#define ORDERCAMD (1<<3)#define EN_V_UP (1<<4)#define EN_V_DOWN (1<<5)#define EN_H_UP (1<<6)#define EN_H_DOWN (1<<7)#define EN_DMA (1<<8)#define THRESHOLD (1<<9)#define THRESHOLD_BIT 9#define THRESHOLD_MASK (0x7f<<9)#define EN_NIRQ (1<<16)#define EN_FIFO_FULL (1<<17)#define RAZ_FIFO (1<<18)/* STATUS bit shifts */#define VSTATUS (1<<0)#define HSTATUS (1<<1)/* GPIO bit shifts */#define CAM_RST (1<<0)/********************* * Watchdog timer. *********************/#define WDTIM_BASE 0xfffec800#define WDTIM_CONTROL (WDTIM_BASE+0x00)#define WDTIM_LOAD (WDTIM_BASE+0x04)#define WDTIM_READ (WDTIM_BASE+0x04)#define WDTIM_MODE (WDTIM_BASE+0x08)/* Values to write to mode register to disable the watchdog function. */#define DISABLE_SEQ1 0xF5#define DISABLE_SEQ2 0xA0/* WDTIM_CONTROL bit definitions. */#define WDTIM_CONTROL_ST BIT7/* --------------------------------------------------------------------------- * Differentiating processor versions for those who care. * --------------------------------------------------------------------------- * */#define OMAP1509 0#define OMAP1510 1#define OMAP1510_ID_CODE_REG 0xfffed404#ifndef __ASSEMBLY__int cpu_type(void);#endif/* * EVM Implementation Specifics. * * *** NOTE *** * Any definitions in these files should be prefixed by an identifier - * eg. OMAP1510P1_FLASH0_BASE . * */#ifdef CONFIG_OMAP_INNOVATOR#include "innovator.h"#endif#ifdef CONFIG_OMAP_1510P1#include "omap1510p1.h"#endif/*****************************************************************************/#define CLKGEN_RESET_BASE (0xfffece00)#define ARM_CKCTL (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0)#define ARM_IDLECT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4)#define ARM_IDLECT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8)#define ARM_EWUPCT (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC)#define ARM_RSTCT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10)#define ARM_RSTCT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14)#define ARM_SYSST (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18)#define CK_CLKIN 12 /* MHz */#define CK_RATEF 1#define CK_IDLEF 2#define CK_ENABLEF 4#define CK_SELECTF 8#ifndef __ASSEMBLER__#define CK_DPLL1 ((volatile __u16 *)0xfffecf00)#else#define CK_DPLL1 (0xfffecf00)#endif#define SETARM_IDLE_SHIFT/* ARM_CKCTL bit shifts */#define PERDIV 0#define LCDDIV 2#define ARMDIV 4#define DSPDIV 6#define TCDIV 8#define DSPMMUDIV 10#define ARM_TIMXO 12#define EN_DSPCK 13#define ARM_INTHCK_SEL 14 /* REVISIT -- where is this used? */#define ARM_CKCTL_RSRVD_BIT15 (1 << 15)#define ARM_CKCTL_ARM_INTHCK_SEL (1 << 14)#define ARM_CKCTL_EN_DSPCK (1 << 13)#define ARM_CKCTL_ARM_TIMXO (1 << 12)#define ARM_CKCTL_DSPMMU_DIV1 (1 << 11)#define ARM_CKCTL_DSPMMU_DIV2 (1 << 10)#define ARM_CKCTL_TCDIV1 (1 << 9)#define ARM_CKCTL_TCDIV2 (1 << 8)#define ARM_CKCTL_DSPDIV1 (1 << 7)#define ARM_CKCTL_DSPDIV0 (1 << 6)#define ARM_CKCTL_ARMDIV1 (1 << 5)#define ARM_CKCTL_ARMDIV0 (1 << 4)#define ARM_CKCTL_LCDDIV1 (1 << 3)#define ARM_CKCTL_LCDDIV0 (1 << 2)#define ARM_CKCTL_PERDIV1 (1 << 1)#define ARM_CKCTL_PERDIV0 (1 << 0)/* ARM_IDLECT1 bit shifts */#define IDLWDT_ARM 0#define IDLXORP_ARM 1#define IDLPER_ARM 2#define IDLLCD_ARM 3#define IDLLB_ARM 4#define IDLHSAB_ARM 5#define IDLIF_ARM 6#define IDLDPLL_ARM 7#define IDLAPI_ARM 8#define IDLTIM_ARM 9#define SETARM_IDLE 11/* ARM_IDLECT2 bit shifts */#define EN_WDTCK 0#define EN_XORPCK 1#define EN_PERCK 2#define EN_LCDCK 3#define EN_LBCK 4#define EN_HSABCK 5#define EN_APICK 6#define EN_TIMCK 7#define DMACK_REQ 8#define EN_GPIOCK 9#define EN_LBFREECK 10#define ARM_RSTCT1_SW_RST (1 << 3)#define ARM_RSTCT1_DSP_RST (1 << 2)#define ARM_RSTCT1_DSP_EN (1 << 1)#define ARM_RSTCT1_ARM_RST (1 << 0)/* ARM_RSTCT2 bit shifts */#define EN_PER 0#define ARM_SYSST_RSRVD_BIT15 (1 << 15)#define ARM_SYSST_RSRVD_BIT14 (1 << 14)#define ARM_SYSST_CLOCK_SELECT2 (1 << 13)#define ARM_SYSST_CLOCK_SELECT1 (1 << 12)#define ARM_SYSST_CLOCK_SELECT0 (1 << 11)#define ARM_SYSST_RSRVD_BIT10 (1 << 10)#define ARM_SYSST_RSRVD_BIT9 (1 << 9)#define ARM_SYSST_RSRVD_BIT8 (1 << 8)#define ARM_SYSST_RSRVD_BIT7 (1 << 7)#define ARM_SYSST_IDLE_DSP (1 << 6)#define ARM_SYSST_POR (1 << 5)#define ARM_SYSST_EXT_RST (1 << 4)#define ARM_SYSST_ARM_MCRST (1 << 3)#define ARM_SYSST_ARM_WDRST (1 << 2)#define ARM_SYSST_GLOB_SWRST (1 << 1)#define ARM_SYSST_DSP_WDRST (1 << 0)/* Table 15-23. DPLL Control Registers: */#define DPLL_CTL_REG (volatile __u16 *)(0xfffecf00)/* Table 15-24. Control Register (CTL_REG): */#define DPLL_CTL_REG_IOB (1 << 13)#define DPLL_CTL_REG_PLL_MULT Fld(5,0)/*****************************************************************************//* OMAP INTERRUPT REGISTERS */#define IRQ_ITR 0x00#define IRQ_MIR 0x04#define IRQ_SIR_IRQ 0x10#define IRQ_SIR_FIQ 0x14#define IRQ_CONTROL_REG 0x18#define IRQ_ISR 0x9c#define IRQ_ILR0 0x1c#define REG_IHL1_MIR (OMAP_IH1_BASE+IRQ_MIR)#define REG_IHL2_MIR (OMAP_IH2_BASE+IRQ_MIR)/* INTERRUPT LEVEL REGISTER BITS */#define ILR_PRIORITY_MASK (0x3c)#define ILR_PRIORITY_SHIFT (2)#define ILR_LEVEL_TRIGGER (1<<1)#define ILR_FIQ (1<<0)#define IRQ_LEVEL_INT 1#define IRQ_EDGE_INT 0/* Macros to access registers */#define outb(v,p) *(volatile u8 *) (p) = v#define outw(v,p) *(volatile u16 *) (p) = v#define outl(v,p) *(volatile u32 *) (p) = v#define inb(p) *(volatile u8 *) (p)#define inw(p) *(volatile u16 *) (p)#define inl(p) *(volatile u32 *) (p)⌨️ 快捷键说明
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