netta2.h

嵌入式试验箱S3C2410的bootloader源代码

#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )

#if CONFIG_NETTA2_VERSION == 2

#define FLASH_BASE4_PRELIM	0x40080000	/* FLASH bank #1	*/

#define CFG_OR4_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR4_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR4_PRELIM	((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )

#endif

/*
 * BR3 and OR3 (SDRAM)
 *
 */
#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)

#define CFG_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)

/*
 * Memory Periodic Timer Prescaler
 */

/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096  Rows from SDRAM example configuration
 * 1000  factor s -> ms
 *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4  Number of refresh cycles per period
 *   64  Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 * 50 MHz => 50.000.000 / Divider =  98
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */

#define CFG_MAMR_PTA		 234

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#define CONFIG_ARTOS			/* include ARTOS support */

#define CONFIG_LAST_STAGE_INIT		/* needed to reset the damn phys */

/****************************************************************/

#define DSP_SIZE	0x00010000	/* 64K */
#define NAND_SIZE	0x00010000	/* 64K */

#define DSP_BASE	0xF1000000
#define NAND_BASE	0xF1010000

/****************************************************************/

/* NAND */
#define CFG_NAND_LEGACY
#define CFG_NAND_BASE		NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_MTD_NAND_UNSAFE

#define CFG_MAX_NAND_DEVICE	1

#define SECTORSIZE		512
#define ADDR_COLUMN		1
#define ADDR_PAGE		2
#define ADDR_COLUMN_PAGE	3
#define NAND_ChipID_UNKNOWN 	0x00
#define NAND_MAX_FLOORS		1
#define NAND_MAX_CHIPS		1

/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
#define NAND_DISABLE_CE(nand) \
	do { \
		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 20)); \
	} while(0)

#define NAND_ENABLE_CE(nand) \
	do { \
		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
	} while(0)

#define NAND_CTL_CLRALE(nandptr) \
	do { \
		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
	} while(0)

#define NAND_CTL_SETALE(nandptr) \
	do { \
		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 17)); \
	} while(0)

#define NAND_CTL_CLRCLE(nandptr) \
	do { \
		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
	} while(0)

#define NAND_CTL_SETCLE(nandptr) \
	do { \
		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 18)); \
	} while(0)

#if CONFIG_NETTA2_VERSION == 1
#define NAND_WAIT_READY(nand) \
	do { \
		int _tries = 0; \
		while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
			if (++_tries > 100000) \
				break; \
	} while (0)
#elif CONFIG_NETTA2_VERSION == 2
#define NAND_WAIT_READY(nand) \
	do { \
		int _tries = 0; \
		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
			if (++_tries > 100000) \
				break; \
	} while (0)
#endif

#define WRITE_NAND_COMMAND(d, adr) \
	do { \
		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
	} while(0)

#define WRITE_NAND_ADDRESS(d, adr) \
	do { \
		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
	} while(0)

#define WRITE_NAND(d, adr) \
	do { \
		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
	} while(0)

#define READ_NAND(adr) \
	((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))

/*****************************************************************************/

#define CFG_DIRECT_FLASH_TFTP
#define CFG_DIRECT_NAND_TFTP

/*****************************************************************************/

#if CONFIG_NETTA2_VERSION == 1
#define STATUS_LED_BIT		0x00000008		/* bit 28 */
#elif CONFIG_NETTA2_VERSION == 2
#define STATUS_LED_BIT		0x00000080		/* bit 24 */
#endif

#define STATUS_LED_PERIOD	(CFG_HZ / 2)
#define STATUS_LED_STATE	STATUS_LED_BLINKING

#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */

#ifndef __ASSEMBLY__

/* LEDs */

/* led_id_t is unsigned int mask */
typedef unsigned int led_id_t;

#define __led_toggle(_msk) \
	do { \
		((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \
	} while(0)

#define __led_set(_msk, _st) \
	do { \
		if ((_st)) \
			((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \
		else \
			((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
	} while(0)

#define __led_init(msk, st) __led_set(msk, st)

#endif

/***********************************************************************************************************

 ----------------------------------------------------------------------------------------------

   (V1) version 1 of the board
   (V2) version 2 of the board

 ----------------------------------------------------------------------------------------------

   Pin definitions:

 +------+----------------+--------+------------------------------------------------------------
 |  #   | Name           | Type   | Comment
 +------+----------------+--------+------------------------------------------------------------
 | PA3  | SPIEN_MAX      | Output | MAX serial to uart chip select
 | PA7  | DSP_INT        | Output | DSP interrupt
 | PA10 | DSP_RESET      | Output | DSP reset
 | PA14 | USBOE          | Output | USB (1)
 | PA15 | USBRXD         | Output | USB (1)
 | PB19 | BT_RTS         | Output | Bluetooth (0)
 | PB23 | BT_CTS         | Output | Bluetooth (0)
 | PB26 | SPIEN_SEP      | Output | Serial EEPROM chip select
 | PB27 | SPICS_DISP     | Output | Display chip select
 | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
 | PB29 | SPI_TXD        | Output | SPI Data Tx
 | PB30 | SPI_CLK        | Output | SPI Clock
 | PC10 | DISPA0         | Output | Display A0
 | PC11 | BACKLIGHT      | Output | Display backlit
 | PC12 | SPI2RXD        | Input  | (V1) 2nd SPI RXD
 |      | IO_RESET       | Output | (V2) General I/O reset
 | PC13 | SPI2TXD        | Output | (V1) 2nd SPI TXD (V1)
 |      | HOOK           | Input  | (V2) Hook input interrupt
 | PC15 | SPI2CLK        | Output | (V1) 2nd SPI CLK
 |      | F_RY_BY        | Input  | (V2) NAND F_RY_BY
 | PE17 | F_ALE          | Output | NAND F_ALE
 | PE18 | F_CLE          | Output | NAND F_CLE
 | PE20 | F_CE           | Output | NAND F_CE
 | PE24 | SPICS_SCOUT    | Output | (V1) Codec chip select
 |      | LED            | Output | (V2) LED
 | PE27 | SPICS_ER       | Output | External serial register CS
 | PE28 | LEDIO1         | Output | (V1) LED
 |      | BKBR1          | Input  | (V2) Keyboard input scan
 | PE29 | LEDIO2         | Output | (V1) LED hook for A (TA2)
 |      | BKBR2          | Input  | (V2) Keyboard input scan
 | PE30 | LEDIO3         | Output | (V1) LED hook for A (TA2)
 |      | BKBR3          | Input  | (V2) Keyboard input scan
 | PE31 | F_RY_BY        | Input  | (V1) NAND F_RY_BY
 |      | BKBR4          | Input  | (V2) Keyboard input scan
 +------+----------------+--------+---------------------------------------------------

 ----------------------------------------------------------------------------------------------

   Serial register input:

 +------+----------------+------------------------------------------------------------
 |  #   | Name           | Comment
 +------+----------------+------------------------------------------------------------
 |    4 | HOOK           | Hook switch
 |    5 | BT_LINK        | Bluetooth link status
 |    6 | HOST_WAKE      | Bluetooth host wake up
 |    7 | OK_ETH         | Cisco inline power OK status
 +------+----------------+------------------------------------------------------------

 ----------------------------------------------------------------------------------------------

 Chip selects:

 +------+----------------+------------------------------------------------------------
 |  #   | Name           | Comment
 +------+----------------+------------------------------------------------------------
 | CS0  | CS0            | Boot flash
 | CS1  | CS_FLASH       | NAND flash
 | CS2  | CS_DSP         | DSP
 | CS3  | DCS_DRAM       | DRAM
 | CS4  | CS_FLASH2      | (V2) 2nd flash
 +------+----------------+------------------------------------------------------------

 ----------------------------------------------------------------------------------------------

 Interrupts:

 +------+----------------+------------------------------------------------------------
 |  #   | Name           | Comment
 +------+----------------+------------------------------------------------------------
 | IRQ1 | IRQ_DSP        | DSP interrupt
 | IRQ3 | S_INTER        | DUSLIC ???
 | IRQ4 | F_RY_BY        | NAND
 | IRQ7 | IRQ_MAX        | MAX 3100 interrupt
 +------+----------------+------------------------------------------------------------

 ----------------------------------------------------------------------------------------------

 Interrupts on PCMCIA pins:

 +------+----------------+------------------------------------------------------------
 |  #   | Name           | Comment
 +------+----------------+------------------------------------------------------------
 | IP_A0| PHY1_LINK      | Link status changed for #1 Ethernet interface
 | IP_A1| PHY2_LINK      | Link status changed for #2 Ethernet interface
 | IP_A2| RMII1_MDINT    | PHY interrupt for #1
 | IP_A3| RMII2_MDINT    | PHY interrupt for #2
 | IP_A5| HOST_WAKE      | (V2) Bluetooth host wake
 | IP_A6| OK_ETH         | (V2) Cisco inline power OK
 +------+----------------+------------------------------------------------------------

**************************************************************************************************/

#define CFG_CONSOLE_IS_IN_ENV		1
#define CFG_CONSOLE_OVERWRITE_ROUTINE	1
#define CFG_CONSOLE_ENV_OVERWRITE	1

/*************************************************************************************************/

/* use board specific hardware */
#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
#define CONFIG_HW_WATCHDOG
#define CONFIG_SHOW_ACTIVITY

/*************************************************************************************************/

#define CONFIG_CDP_DEVICE_ID		20
#define CONFIG_CDP_DEVICE_ID_PREFIX	"NT"	/* netta2 */
#define CONFIG_CDP_PORT_ID		"eth%d"
#define CONFIG_CDP_CAPABILITIES		0x00000010
#define CONFIG_CDP_VERSION		"u-boot" " " __DATE__ " " __TIME__
#define CONFIG_CDP_PLATFORM		"Intracom NetTA2"
#define CONFIG_CDP_TRIGGER		0x20020001
#define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
#define CONFIG_CDP_APPLIANCE_VLAN_TYPE	0x01	/* ipphone ? */

/*************************************************************************************************/

#define CONFIG_AUTO_COMPLETE	1

/*************************************************************************************************/

#define CONFIG_CRC32_VERIFY	1

/*************************************************************************************************/

#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1

/*************************************************************************************************/
#endif	/* __CONFIG_H */