📄 inca-ip.h
字号:
#define INCA_IP_Switch_PMAC_DA2 ((volatile u32*)(INCA_IP_Switch+ 0x0290))#define INCA_IP_Switch_PMAC_DA2_DA_31_0/***PM VLAN Register***/#define INCA_IP_Switch_PMAC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0294))#define INCA_IP_Switch_PMAC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 13)#define INCA_IP_Switch_PMAC_VLAN_CFI (1 << 12)#define INCA_IP_Switch_PMAC_VLAN_VLANID (value) (((( 1 << 12) - 1) & (value)) << 0)/***PM TX IPG Counter Register***/#define INCA_IP_Switch_PMAC_TX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x0298))#define INCA_IP_Switch_PMAC_TX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0)/***PM RX IPG Counter Register***/#define INCA_IP_Switch_PMAC_RX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x029C))#define INCA_IP_Switch_PMAC_RX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0)/***Mirror Register***/#define INCA_IP_Switch_MRR ((volatile u32*)(INCA_IP_Switch+ 0x0300))#define INCA_IP_Switch_MRR_MRR (value) (((( 1 << 2) - 1) & (value)) << 6)#define INCA_IP_Switch_MRR_EC (1 << 5)#define INCA_IP_Switch_MRR_EL (1 << 4)#define INCA_IP_Switch_MRR_EP (1 << 3)#define INCA_IP_Switch_MRR_IC (1 << 2)#define INCA_IP_Switch_MRR_IL (1 << 1)#define INCA_IP_Switch_MRR_IP (1 << 0)/***Packet Length Register***/#define INCA_IP_Switch_PKT_LEN ((volatile u32*)(INCA_IP_Switch+ 0x0304))#define INCA_IP_Switch_PKT_LEN_ADD (1 << 11)#define INCA_IP_Switch_PKT_LEN_MAX_PKT_LEN (value) (((( 1 << 11) - 1) & (value)) << 0)/***MDIO Access Register***/#define INCA_IP_Switch_MDIO_ACC ((volatile u32*)(INCA_IP_Switch+ 0x0480))#define INCA_IP_Switch_MDIO_ACC_RA (1 << 31)#define INCA_IP_Switch_MDIO_ACC_RW (1 << 30)#define INCA_IP_Switch_MDIO_ACC_PHY_ADDR (value) (((( 1 << 5) - 1) & (value)) << 21)#define INCA_IP_Switch_MDIO_ACC_REG_ADDR (value) (((( 1 << 5) - 1) & (value)) << 16)#define INCA_IP_Switch_MDIO_ACC_PHY_DATA (value) (((( 1 << 16) - 1) & (value)) << 0)/***Ethernet PHY Register***/#define INCA_IP_Switch_EPHY ((volatile u32*)(INCA_IP_Switch+ 0x0484))#define INCA_IP_Switch_EPHY_SL (1 << 7)#define INCA_IP_Switch_EPHY_SP (1 << 6)#define INCA_IP_Switch_EPHY_LL (1 << 5)#define INCA_IP_Switch_EPHY_LP (1 << 4)#define INCA_IP_Switch_EPHY_DL (1 << 3)#define INCA_IP_Switch_EPHY_DP (1 << 2)#define INCA_IP_Switch_EPHY_PL (1 << 1)#define INCA_IP_Switch_EPHY_PP (1 << 0)/***Pause Write Enable Register***/#define INCA_IP_Switch_PWR_EN ((volatile u32*)(INCA_IP_Switch+ 0x0488))#define INCA_IP_Switch_PWR_EN_PL (1 << 1)#define INCA_IP_Switch_PWR_EN_PP (1 << 0)/***MDIO Configuration Register***/#define INCA_IP_Switch_MDIO_CFG ((volatile u32*)(INCA_IP_Switch+ 0x048C))#define INCA_IP_Switch_MDIO_CFG_MDS (value) (((( 1 << 2) - 1) & (value)) << 14)#define INCA_IP_Switch_MDIO_CFG_PHY_LAN_ADDR (value) (((( 1 << 5) - 1) & (value)) << 9)#define INCA_IP_Switch_MDIO_CFG_PHY_PC_ADDR (value) (((( 1 << 5) - 1) & (value)) << 4)#define INCA_IP_Switch_MDIO_CFG_UEP (1 << 3)#define INCA_IP_Switch_MDIO_CFG_PS (1 << 2)#define INCA_IP_Switch_MDIO_CFG_PT (1 << 1)#define INCA_IP_Switch_MDIO_CFG_UMM (1 << 0)/***Clock Configuration Register***/#define INCA_IP_Switch_CLK_CFG ((volatile u32*)(INCA_IP_Switch+ 0x0500))#define INCA_IP_Switch_CLK_CFG_ARL_ID (1 << 9)#define INCA_IP_Switch_CLK_CFG_CPU_ID (1 << 8)#define INCA_IP_Switch_CLK_CFG_LAN_ID (1 << 7)#define INCA_IP_Switch_CLK_CFG_PC_ID (1 << 6)#define INCA_IP_Switch_CLK_CFG_SE_ID (1 << 5)/***********************************************************************//* Module : SSC1 register address and bits *//***********************************************************************/#define INCA_IP_SSC1 (0xB8000500)/***********************************************************************//***Control Register (Programming Mode)***/#define INCA_IP_SSC1_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC1+ 0x0010))#define INCA_IP_SSC1_SCC_CON_PRG_EN (1 << 15)#define INCA_IP_SSC1_SCC_CON_PRG_MS (1 << 14)#define INCA_IP_SSC1_SCC_CON_PRG_AREN (1 << 12)#define INCA_IP_SSC1_SCC_CON_PRG_BEN (1 << 11)#define INCA_IP_SSC1_SCC_CON_PRG_PEN (1 << 10)#define INCA_IP_SSC1_SCC_CON_PRG_REN (1 << 9)#define INCA_IP_SSC1_SCC_CON_PRG_TEN (1 << 8)#define INCA_IP_SSC1_SCC_CON_PRG_LB (1 << 7)#define INCA_IP_SSC1_SCC_CON_PRG_PO (1 << 6)#define INCA_IP_SSC1_SCC_CON_PRG_PH (1 << 5)#define INCA_IP_SSC1_SCC_CON_PRG_HB (1 << 4)#define INCA_IP_SSC1_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0)/***SCC Control Register (Operating Mode)***/#define INCA_IP_SSC1_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC1+ 0x0010))#define INCA_IP_SSC1_SCC_CON_OPR_EN (1 << 15)#define INCA_IP_SSC1_SCC_CON_OPR_MS (1 << 14)#define INCA_IP_SSC1_SCC_CON_OPR_BSY (1 << 12)#define INCA_IP_SSC1_SCC_CON_OPR_BE (1 << 11)#define INCA_IP_SSC1_SCC_CON_OPR_PE (1 << 10)#define INCA_IP_SSC1_SCC_CON_OPR_RE (1 << 9)#define INCA_IP_SSC1_SCC_CON_OPR_TE (1 << 8)#define INCA_IP_SSC1_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0)/***SSC Write Hardware Modified Control Register***/#define INCA_IP_SSC1_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC1+ 0x0040))#define INCA_IP_SSC1_SSC_WHBCON_SETBE (1 << 15)#define INCA_IP_SSC1_SSC_WHBCON_SETPE (1 << 14)#define INCA_IP_SSC1_SSC_WHBCON_SETRE (1 << 13)#define INCA_IP_SSC1_SSC_WHBCON_SETTE (1 << 12)#define INCA_IP_SSC1_SSC_WHBCON_CLRBE (1 << 11)#define INCA_IP_SSC1_SSC_WHBCON_CLRPE (1 << 10)#define INCA_IP_SSC1_SSC_WHBCON_CLRRE (1 << 9)#define INCA_IP_SSC1_SSC_WHBCON_CLRTE (1 << 8)/***SSC Baudrate Timer Reload Register***/#define INCA_IP_SSC1_SSC_BR ((volatile u32*)(INCA_IP_SSC1+ 0x0014))#define INCA_IP_SSC1_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)/***SSC Transmitter Buffer Register***/#define INCA_IP_SSC1_SSC_TB ((volatile u32*)(INCA_IP_SSC1+ 0x0020))#define INCA_IP_SSC1_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)/***SSC Receiver Buffer Register***/#define INCA_IP_SSC1_SSC_RB ((volatile u32*)(INCA_IP_SSC1+ 0x0024))#define INCA_IP_SSC1_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)/***SSC Receive FIFO Control Register***/#define INCA_IP_SSC1_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0030))#define INCA_IP_SSC1_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)#define INCA_IP_SSC1_SSC_RXFCON_RXTMEN (1 << 2)#define INCA_IP_SSC1_SSC_RXFCON_RXFLU (1 << 1)#define INCA_IP_SSC1_SSC_RXFCON_RXFEN (1 << 0)/***SSC Transmit FIFO Control Register***/#define INCA_IP_SSC1_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0034))#define INCA_IP_SSC1_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)#define INCA_IP_SSC1_SSC_TXFCON_TXTMEN (1 << 2)#define INCA_IP_SSC1_SSC_TXFCON_TXFLU (1 << 1)#define INCA_IP_SSC1_SSC_TXFCON_TXFEN (1 << 0)/***SSC FIFO Status Register***/#define INCA_IP_SSC1_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC1+ 0x0038))#define INCA_IP_SSC1_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8)#define INCA_IP_SSC1_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0)/***SSC Clock Control Register***/#define INCA_IP_SSC1_SSC_CLC ((volatile u32*)(INCA_IP_SSC1+ 0x0000))#define INCA_IP_SSC1_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)#define INCA_IP_SSC1_SSC_CLC_DISS (1 << 1)#define INCA_IP_SSC1_SSC_CLC_DISR (1 << 0)/***********************************************************************//* Module : SSC2 register address and bits *//***********************************************************************/#define INCA_IP_SSC2 (0xB8000600)/***********************************************************************//***Control Register (Programming Mode)***/#define INCA_IP_SSC2_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC2+ 0x0010))#define INCA_IP_SSC2_SCC_CON_PRG_EN (1 << 15)#define INCA_IP_SSC2_SCC_CON_PRG_MS (1 << 14)#define INCA_IP_SSC2_SCC_CON_PRG_AREN (1 << 12)#define INCA_IP_SSC2_SCC_CON_PRG_BEN (1 << 11)#define INCA_IP_SSC2_SCC_CON_PRG_PEN (1 << 10)#define INCA_IP_SSC2_SCC_CON_PRG_REN (1 << 9)#define INCA_IP_SSC2_SCC_CON_PRG_TEN (1 << 8)#define INCA_IP_SSC2_SCC_CON_PRG_LB (1 << 7)#define INCA_IP_SSC2_SCC_CON_PRG_PO (1 << 6)#define INCA_IP_SSC2_SCC_CON_PRG_PH (1 << 5)#define INCA_IP_SSC2_SCC_CON_PRG_HB (1 << 4)#define INCA_IP_SSC2_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0)/***SCC Control Register (Operating Mode)***/#define INCA_IP_SSC2_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC2+ 0x0010))#define INCA_IP_SSC2_SCC_CON_OPR_EN (1 << 15)#define INCA_IP_SSC2_SCC_CON_OPR_MS (1 << 14)#define INCA_IP_SSC2_SCC_CON_OPR_BSY (1 << 12)#define INCA_IP_SSC2_SCC_CON_OPR_BE (1 << 11)#define INCA_IP_SSC2_SCC_CON_OPR_PE (1 << 10)#define INCA_IP_SSC2_SCC_CON_OPR_RE (1 << 9)#define INCA_IP_SSC2_SCC_CON_OPR_TE (1 << 8)#define INCA_IP_SSC2_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0)/***SSC Write Hardware Modified Control Register***/#define INCA_IP_SSC2_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC2+ 0x0040))#define INCA_IP_SSC2_SSC_WHBCON_SETBE (1 << 15)#define INCA_IP_SSC2_SSC_WHBCON_SETPE (1 << 14)#define INCA_IP_SSC2_SSC_WHBCON_SETRE (1 << 13)#define INCA_IP_SSC2_SSC_WHBCON_SETTE (1 << 12)#define INCA_IP_SSC2_SSC_WHBCON_CLRBE (1 << 11)#define INCA_IP_SSC2_SSC_WHBCON_CLRPE (1 << 10)#define INCA_IP_SSC2_SSC_WHBCON_CLRRE (1 << 9)#define INCA_IP_SSC2_SSC_WHBCON_CLRTE (1 << 8)/***SSC Baudrate Timer Reload Register***/#define INCA_IP_SSC2_SSC_BR ((volatile u32*)(INCA_IP_SSC2+ 0x0014))#define INCA_IP_SSC2_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)/***SSC Transmitter Buffer Register***/#define INCA_IP_SSC2_SSC_TB ((volatile u32*)(INCA_IP_SSC2+ 0x0020))#define INCA_IP_SSC2_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)/***SSC Receiver Buffer Register***/#define INCA_IP_SSC2_SSC_RB ((volatile u32*)(INCA_IP_SSC2+ 0x0024))#define INCA_IP_SSC2_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)/***SSC Receive FIFO Control Register***/#define INCA_IP_SSC2_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0030))#define INCA_IP_SSC2_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)#define INCA_IP_SSC2_SSC_RXFCON_RXTMEN (1 << 2)#define INCA_IP_SSC2_SSC_RXFCON_RXFLU (1 << 1)⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -