📄 au1x00.h
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* These are the definitions for the Modem Status Register */#define UART_MSR_DCD 0x80 /* Data Carrier Detect */#define UART_MSR_RI 0x40 /* Ring Indicator */#define UART_MSR_DSR 0x20 /* Data Set Ready */#define UART_MSR_CTS 0x10 /* Clear to Send */#define UART_MSR_DDCD 0x08 /* Delta DCD */#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */#define UART_MSR_DDSR 0x02 /* Delta DSR */#define UART_MSR_DCTS 0x01 /* Delta CTS */#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! *//* SSIO */#define SSI0_STATUS 0xB1600000#define SSI_STATUS_BF (1<<4)#define SSI_STATUS_OF (1<<3)#define SSI_STATUS_UF (1<<2)#define SSI_STATUS_D (1<<1)#define SSI_STATUS_B (1<<0)#define SSI0_INT 0xB1600004#define SSI_INT_OI (1<<3)#define SSI_INT_UI (1<<2)#define SSI_INT_DI (1<<1)#define SSI0_INT_ENABLE 0xB1600008#define SSI_INTE_OIE (1<<3)#define SSI_INTE_UIE (1<<2)#define SSI_INTE_DIE (1<<1)#define SSI0_CONFIG 0xB1600020#define SSI_CONFIG_AO (1<<24)#define SSI_CONFIG_DO (1<<23)#define SSI_CONFIG_ALEN_BIT 20#define SSI_CONFIG_ALEN_MASK (0x7<<20)#define SSI_CONFIG_DLEN_BIT 16#define SSI_CONFIG_DLEN_MASK (0x7<<16)#define SSI_CONFIG_DD (1<<11)#define SSI_CONFIG_AD (1<<10)#define SSI_CONFIG_BM_BIT 8#define SSI_CONFIG_BM_MASK (0x3<<8)#define SSI_CONFIG_CE (1<<7)#define SSI_CONFIG_DP (1<<6)#define SSI_CONFIG_DL (1<<5)#define SSI_CONFIG_EP (1<<4)#define SSI0_ADATA 0xB1600024#define SSI_AD_D (1<<24)#define SSI_AD_ADDR_BIT 16#define SSI_AD_ADDR_MASK (0xff<<16)#define SSI_AD_DATA_BIT 0#define SSI_AD_DATA_MASK (0xfff<<0)#define SSI0_CLKDIV 0xB1600028#define SSI0_CONTROL 0xB1600100#define SSI_CONTROL_CD (1<<1)#define SSI_CONTROL_E (1<<0)/* SSI1 */#define SSI1_STATUS 0xB1680000#define SSI1_INT 0xB1680004#define SSI1_INT_ENABLE 0xB1680008#define SSI1_CONFIG 0xB1680020#define SSI1_ADATA 0xB1680024#define SSI1_CLKDIV 0xB1680028#define SSI1_ENABLE 0xB1680100/* * Register content definitions */#define SSI_STATUS_BF (1<<4)#define SSI_STATUS_OF (1<<3)#define SSI_STATUS_UF (1<<2)#define SSI_STATUS_D (1<<1)#define SSI_STATUS_B (1<<0)/* SSI_INT */#define SSI_INT_OI (1<<3)#define SSI_INT_UI (1<<2)#define SSI_INT_DI (1<<1)/* SSI_INTEN */#define SSI_INTEN_OIE (1<<3)#define SSI_INTEN_UIE (1<<2)#define SSI_INTEN_DIE (1<<1)#define SSI_CONFIG_AO (1<<24)#define SSI_CONFIG_DO (1<<23)#define SSI_CONFIG_ALEN (7<<20)#define SSI_CONFIG_DLEN (15<<16)#define SSI_CONFIG_DD (1<<11)#define SSI_CONFIG_AD (1<<10)#define SSI_CONFIG_BM (3<<8)#define SSI_CONFIG_CE (1<<7)#define SSI_CONFIG_DP (1<<6)#define SSI_CONFIG_DL (1<<5)#define SSI_CONFIG_EP (1<<4)#define SSI_CONFIG_ALEN_N(N) ((N-1)<<20)#define SSI_CONFIG_DLEN_N(N) ((N-1)<<16)#define SSI_CONFIG_BM_HI (0<<8)#define SSI_CONFIG_BM_LO (1<<8)#define SSI_CONFIG_BM_CY (2<<8)#define SSI_ADATA_D (1<<24)#define SSI_ADATA_ADDR (0xFF<<16)#define SSI_ADATA_DATA (0x0FFF)#define SSI_ADATA_ADDR_N(N) (N<<16)#define SSI_ENABLE_CD (1<<1)#define SSI_ENABLE_E (1<<0)/* IrDA Controller */#define IRDA_BASE 0xB0300000#define IR_RING_PTR_STATUS (IRDA_BASE+0x00)#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)#define IR_RING_SIZE (IRDA_BASE+0x0C)#define IR_RING_PROMPT (IRDA_BASE+0x10)#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)#define IR_INT_CLEAR (IRDA_BASE+0x18)#define IR_CONFIG_1 (IRDA_BASE+0x20)#define IR_RX_INVERT_LED (1<<0)#define IR_TX_INVERT_LED (1<<1)#define IR_ST (1<<2)#define IR_SF (1<<3)#define IR_SIR (1<<4)#define IR_MIR (1<<5)#define IR_FIR (1<<6)#define IR_16CRC (1<<7)#define IR_TD (1<<8)#define IR_RX_ALL (1<<9)#define IR_DMA_ENABLE (1<<10)#define IR_RX_ENABLE (1<<11)#define IR_TX_ENABLE (1<<12)#define IR_LOOPBACK (1<<14)#define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)#define IR_SIR_FLAGS (IRDA_BASE+0x24)#define IR_ENABLE (IRDA_BASE+0x28)#define IR_RX_STATUS (1<<9)#define IR_TX_STATUS (1<<10)#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)#define IR_MAX_PKT_LEN (IRDA_BASE+0x34)#define IR_RX_BYTE_CNT (IRDA_BASE+0x38)#define IR_CONFIG_2 (IRDA_BASE+0x3C)#define IR_MODE_INV (1<<0)#define IR_ONE_PIN (1<<1)#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)/* GPIO */#define SYS_PINFUNC 0xB190002C#define SYS_PF_USB (1<<15) /* 2nd USB device/host */#define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */#define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */#define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */#define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */#define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */#define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */#define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */#define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */#define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */#define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */#define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */#define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */#define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */#define SYS_PF_A97 (1<<1) /* AC97/SSL1 */#define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */#define SYS_TRIOUTRD 0xB1900100#define SYS_TRIOUTCLR 0xB1900100#define SYS_OUTPUTRD 0xB1900108#define SYS_OUTPUTSET 0xB1900108#define SYS_OUTPUTCLR 0xB190010C#define SYS_PINSTATERD 0xB1900110#define SYS_PININPUTEN 0xB1900110/* GPIO2, Au1500 only */#define GPIO2_BASE 0xB1700000#define GPIO2_DIR (GPIO2_BASE + 0)#define GPIO2_DATA_EN (GPIO2_BASE + 8)#define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)#define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)#define GPIO2_ENABLE (GPIO2_BASE + 0x14)/* Power Management */#define SYS_SCRATCH0 0xB1900018#define SYS_SCRATCH1 0xB190001C#define SYS_WAKEMSK 0xB1900034#define SYS_ENDIAN 0xB1900038#define SYS_POWERCTRL 0xB190003C#define SYS_WAKESRC 0xB190005C#define SYS_SLPPWR 0xB1900078#define SYS_SLEEP 0xB190007C/* Clock Controller */#define SYS_FREQCTRL0 0xB1900020#define SYS_FC_FRDIV2_BIT 22#define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT)#define SYS_FC_FE2 (1<<21)#define SYS_FC_FS2 (1<<20)#define SYS_FC_FRDIV1_BIT 12#define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT)#define SYS_FC_FE1 (1<<11)#define SYS_FC_FS1 (1<<10)#define SYS_FC_FRDIV0_BIT 2#define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT)#define SYS_FC_FE0 (1<<1)#define SYS_FC_FS0 (1<<0)#define SYS_FREQCTRL1 0xB1900024#define SYS_FC_FRDIV5_BIT 22#define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT)#define SYS_FC_FE5 (1<<21)#define SYS_FC_FS5 (1<<20)#define SYS_FC_FRDIV4_BIT 12#define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT)#define SYS_FC_FE4 (1<<11)#define SYS_FC_FS4 (1<<10)#define SYS_FC_FRDIV3_BIT 2#define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT)#define SYS_FC_FE3 (1<<1)#define SYS_FC_FS3 (1<<0)#define SYS_CLKSRC 0xB1900028#define SYS_CS_ME1_BIT 27#define SYS_CS_ME1_MASK (0x7<<CSC_ME1_BIT)#define SYS_CS_DE1 (1<<26)#define SYS_CS_CE1 (1<<25)#define SYS_CS_ME0_BIT 22#define SYS_CS_ME0_MASK (0x7<<CSC_ME0_BIT)#define SYS_CS_DE0 (1<<21)#define SYS_CS_CE0 (1<<20)#define SYS_CS_MI2_BIT 17#define SYS_CS_MI2_MASK (0x7<<CSC_MI2_BIT)#define SYS_CS_DI2 (1<<16)#define SYS_CS_CI2 (1<<15)#define SYS_CS_MUH_BIT 12#define SYS_CS_MUH_MASK (0x7<<CSC_MUH_BIT)#define SYS_CS_DUH (1<<11)#define SYS_CS_CUH (1<<10)#define SYS_CS_MUD_BIT 7#define SYS_CS_MUD_MASK (0x7<<CSC_MUD_BIT)#define SYS_CS_DUD (1<<6)#define SYS_CS_CUD (1<<5)#define SYS_CS_MIR_BIT 2#define SYS_CS_MIR_MASK (0x7<<CSC_MIR_BIT)#define SYS_CS_DIR (1<<1)#define SYS_CS_CIR (1<<0)#define SYS_CS_MUX_AUX 0x1#define SYS_CS_MUX_FQ0 0x2#define SYS_CS_MUX_FQ1 0x3#define SYS_CS_MUX_FQ2 0x4#define SYS_CS_MUX_FQ3 0x5#define SYS_CS_MUX_FQ4 0x6#define SYS_CS_MUX_FQ5 0x7#define SYS_CPUPLL 0xB1900060#define SYS_AUXPLL 0xB1900064/* AC97 Controller */#define AC97C_CONFIG 0xB0000000#define AC97C_RECV_SLOTS_BIT 13#define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)#define AC97C_XMIT_SLOTS_BIT 3#define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)#define AC97C_SG (1<<2)#define AC97C_SYNC (1<<1)#define AC97C_RESET (1<<0)#define AC97C_STATUS 0xB0000004#define AC97C_XU (1<<11)#define AC97C_XO (1<<10)#define AC97C_RU (1<<9)#define AC97C_RO (1<<8)#define AC97C_READY (1<<7)#define AC97C_CP (1<<6)#define AC97C_TR (1<<5)#define AC97C_TE (1<<4)#define AC97C_TF (1<<3)#define AC97C_RR (1<<2)#define AC97C_RE (1<<1)#define AC97C_RF (1<<0)#define AC97C_DATA 0xB0000008#define AC97C_CMD 0xB000000C#define AC97C_WD_BIT 16#define AC97C_READ (1<<7)#define AC97C_INDEX_MASK 0x7f#define AC97C_CNTRL 0xB0000010#define AC97C_RS (1<<1)#define AC97C_CE (1<<0)#define DB1000_BCSR_ADDR 0xAE000000#define DB1550_BCSR_ADDR 0xAF000000#ifdef CONFIG_DBAU1550#define DB1XX0_BCSR_ADDR DB1550_BCSR_ADDR#else#define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR#endif#ifdef CONFIG_SOC_AU1500/* Au1500 PCI Controller */#define Au1500_CFG_BASE 0xB4005000 /* virtual, kseg0 addr */#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)#define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)#define Au1500_PCI_HDR 0xB4005100 /* virtual, kseg0 addr *//* All of our structures, like pci resource, have 32 bit members. * Drivers are expected to do an ioremap on the PCI MEM resource, but it's * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM * addresses. For PCI IO, it's simpler because we get to do the ioremap * ourselves and then adjust the device's resources. */#define Au1500_EXT_CFG 0x600000000#define Au1500_EXT_CFG_TYPE1 0x680000000#define Au1500_PCI_IO_START 0x500000000#define Au1500_PCI_IO_END 0x5000FFFFF#define Au1500_PCI_MEM_START 0x440000000#define Au1500_PCI_MEM_END 0x443FFFFFF#define PCI_IO_START (Au1500_PCI_IO_START + 0x300)#define PCI_IO_END (Au1500_PCI_IO_END)#define PCI_MEM_START (Au1500_PCI_MEM_START)#define PCI_MEM_END (Au1500_PCI_MEM_END)#define PCI_FIRST_DEVFN (0<<3)#define PCI_LAST_DEVFN (19<<3)#endif#if defined(CONFIG_SOC_AU1100) || (defined(CONFIG_SOC_AU1000) && !defined(CONFIG_MIPS_PB1000))/* no PCI bus controller */#define PCI_IO_START 0#define PCI_IO_END 0#define PCI_MEM_START 0#define PCI_MEM_END 0#define PCI_FIRST_DEVFN 0#define PCI_LAST_DEVFN 0#endif#define AU1X_SOCK0_IO 0xF00000000#define AU1X_SOCK0_PHYS_ATTR 0xF40000000#define AU1X_SOCK0_PHYS_MEM 0xF80000000/* pcmcia socket 1 needs external glue logic so the memory map * differs from board to board. *//* Only for db board, not older pb */#define AU1X_SOCK1_IO 0xF04000000#define AU1X_SOCK1_PHYS_ATTR 0xF44000000#define AU1X_SOCK1_PHYS_MEM 0xF84000000#endif⌨️ 快捷键说明
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