au1x00.h

嵌入式试验箱S3C2410的bootloader源代码

#define AU1500_GPIO_23            55
#define AU1500_GPIO_24            56
#define AU1500_GPIO_25            57
#define AU1500_GPIO_26            58
#define AU1500_GPIO_27            59
#define AU1500_GPIO_28            60
#define AU1500_GPIO_206           61
#define AU1500_GPIO_207           62
#define AU1500_GPIO_208_215       63

#define AU1X00_MAX_INTR           63

#define AU1100_SD		2
#define	AU1100_GPIO_208_215	29
/* REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE */

/* Programmable Counters 0 and 1 */
#define SYS_BASE                   0xB1900000
#define SYS_COUNTER_CNTRL          (SYS_BASE + 0x14)
#define SYS_CNTRL_E1S            (1<<23)
#define SYS_CNTRL_T1S            (1<<20)
#define SYS_CNTRL_M21            (1<<19)
#define SYS_CNTRL_M11            (1<<18)
#define SYS_CNTRL_M01            (1<<17)
#define SYS_CNTRL_C1S            (1<<16)
#define SYS_CNTRL_BP             (1<<14)
#define SYS_CNTRL_EN1            (1<<13)
#define SYS_CNTRL_BT1            (1<<12)
#define SYS_CNTRL_EN0            (1<<11)
#define SYS_CNTRL_BT0            (1<<10)
#define SYS_CNTRL_E0             (1<<8)
#define SYS_CNTRL_E0S            (1<<7)
#define SYS_CNTRL_32S            (1<<5)
#define SYS_CNTRL_T0S            (1<<4)
#define SYS_CNTRL_M20            (1<<3)
#define SYS_CNTRL_M10            (1<<2)
#define SYS_CNTRL_M00            (1<<1)
#define SYS_CNTRL_C0S            (1<<0)

/* Programmable Counter 0 Registers */
#define SYS_TOYTRIM                 (SYS_BASE + 0)
#define SYS_TOYWRITE                (SYS_BASE + 4)
#define SYS_TOYMATCH0               (SYS_BASE + 8)
#define SYS_TOYMATCH1               (SYS_BASE + 0xC)
#define SYS_TOYMATCH2               (SYS_BASE + 0x10)
#define SYS_TOYREAD                 (SYS_BASE + 0x40)

/* Programmable Counter 1 Registers */
#define SYS_RTCTRIM                 (SYS_BASE + 0x44)
#define SYS_RTCWRITE                (SYS_BASE + 0x48)
#define SYS_RTCMATCH0               (SYS_BASE + 0x4C)
#define SYS_RTCMATCH1               (SYS_BASE + 0x50)
#define SYS_RTCMATCH2               (SYS_BASE + 0x54)
#define SYS_RTCREAD                 (SYS_BASE + 0x58)

/* I2S Controller */
#define I2S_DATA                    0xB1000000
#define I2S_DATA_MASK        (0xffffff)
#define I2S_CONFIG                0xB1000004
#define I2S_CONFIG_XU        (1<<25)
#define I2S_CONFIG_XO        (1<<24)
#define I2S_CONFIG_RU        (1<<23)
#define I2S_CONFIG_RO        (1<<22)
#define I2S_CONFIG_TR        (1<<21)
#define I2S_CONFIG_TE        (1<<20)
#define I2S_CONFIG_TF        (1<<19)
#define I2S_CONFIG_RR        (1<<18)
#define I2S_CONFIG_RE        (1<<17)
#define I2S_CONFIG_RF        (1<<16)
#define I2S_CONFIG_PD        (1<<11)
#define I2S_CONFIG_LB        (1<<10)
#define I2S_CONFIG_IC        (1<<9)
#define I2S_CONFIG_FM_BIT    7
#define I2S_CONFIG_FM_MASK     (0x3 << I2S_CONFIG_FM_BIT)
#define I2S_CONFIG_FM_I2S    (0x0 << I2S_CONFIG_FM_BIT)
#define I2S_CONFIG_FM_LJ     (0x1 << I2S_CONFIG_FM_BIT)
#define I2S_CONFIG_FM_RJ     (0x2 << I2S_CONFIG_FM_BIT)
#define I2S_CONFIG_TN        (1<<6)
#define I2S_CONFIG_RN        (1<<5)
#define I2S_CONFIG_SZ_BIT    0
#define I2S_CONFIG_SZ_MASK     (0x1F << I2S_CONFIG_SZ_BIT)

#define I2S_CONTROL                0xB1000008
#define I2S_CONTROL_D         (1<<1)
#define I2S_CONTROL_CE        (1<<0)

/* USB Host Controller */
/* We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address */
#define USB_OHCI_BASE             0x10100000
#define USB_OHCI_LEN              0x00100000
#define USB_HOST_CONFIG           0xB017fffc

/* USB Device Controller */
#define USBD_EP0RD                0xB0200000
#define USBD_EP0WR                0xB0200004
#define USBD_EP2WR                0xB0200008
#define USBD_EP3WR                0xB020000C
#define USBD_EP4RD                0xB0200010
#define USBD_EP5RD                0xB0200014
#define USBD_INTEN                0xB0200018
#define USBD_INTSTAT              0xB020001C
#define USBDEV_INT_SOF       (1<<12)
#define USBDEV_INT_HF_BIT    6
#define USBDEV_INT_HF_MASK   (0x3f << USBDEV_INT_HF_BIT)
#define USBDEV_INT_CMPLT_BIT  0
#define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
#define USBD_CONFIG               0xB0200020
#define USBD_EP0CS                0xB0200024
#define USBD_EP2CS                0xB0200028
#define USBD_EP3CS                0xB020002C
#define USBD_EP4CS                0xB0200030
#define USBD_EP5CS                0xB0200034
#define USBDEV_CS_SU         (1<<14)
#define USBDEV_CS_NAK        (1<<13)
#define USBDEV_CS_ACK        (1<<12)
#define USBDEV_CS_BUSY       (1<<11)
#define USBDEV_CS_TSIZE_BIT  1
#define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
#define USBDEV_CS_STALL      (1<<0)
#define USBD_EP0RDSTAT            0xB0200040
#define USBD_EP0WRSTAT            0xB0200044
#define USBD_EP2WRSTAT            0xB0200048
#define USBD_EP3WRSTAT            0xB020004C
#define USBD_EP4RDSTAT            0xB0200050
#define USBD_EP5RDSTAT            0xB0200054
#define USBDEV_FSTAT_FLUSH     (1<<6)
#define USBDEV_FSTAT_UF        (1<<5)
#define USBDEV_FSTAT_OF        (1<<4)
#define USBDEV_FSTAT_FCNT_BIT  0
#define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
#define USBD_ENABLE               0xB0200058
#define USBDEV_ENABLE (1<<1)
#define USBDEV_CE     (1<<0)

/* Ethernet Controllers  */
#define AU1000_ETH0_BASE          0xB0500000
#define AU1000_ETH1_BASE          0xB0510000
#define AU1500_ETH0_BASE	  0xB1500000
#define AU1500_ETH1_BASE	  0xB1510000
#define AU1100_ETH0_BASE	  0xB0500000
#define AU1550_ETH0_BASE	  0xB0500000
#define AU1550_ETH1_BASE	  0xB0510000

/* 4 byte offsets from AU1000_ETH_BASE */
#define MAC_CONTROL                     0x0
#define MAC_RX_ENABLE               (1<<2)
#define MAC_TX_ENABLE               (1<<3)
#define MAC_DEF_CHECK               (1<<5)
#define MAC_SET_BL(X)       (((X)&0x3)<<6)
#define MAC_AUTO_PAD                (1<<8)
#define MAC_DISABLE_RETRY          (1<<10)
#define MAC_DISABLE_BCAST          (1<<11)
#define MAC_LATE_COL               (1<<12)
#define MAC_HASH_MODE              (1<<13)
#define MAC_HASH_ONLY              (1<<15)
#define MAC_PASS_ALL               (1<<16)
#define MAC_INVERSE_FILTER         (1<<17)
#define MAC_PROMISCUOUS            (1<<18)
#define MAC_PASS_ALL_MULTI         (1<<19)
#define MAC_FULL_DUPLEX            (1<<20)
#define MAC_NORMAL_MODE                 0
#define MAC_INT_LOOPBACK           (1<<21)
#define MAC_EXT_LOOPBACK           (1<<22)
#define MAC_DISABLE_RX_OWN         (1<<23)
#define MAC_BIG_ENDIAN             (1<<30)
#define MAC_RX_ALL                 (1<<31)
#define MAC_ADDRESS_HIGH                0x4
#define MAC_ADDRESS_LOW                 0x8
#define MAC_MCAST_HIGH                  0xC
#define MAC_MCAST_LOW                  0x10
#define MAC_MII_CNTRL                  0x14
#define MAC_MII_BUSY                (1<<0)
#define MAC_MII_READ                     0
#define MAC_MII_WRITE               (1<<1)
#define MAC_SET_MII_SELECT_REG(X)   (((X)&0x1f)<<6)
#define MAC_SET_MII_SELECT_PHY(X)   (((X)&0x1f)<<11)
#define MAC_MII_DATA                   0x18
#define MAC_FLOW_CNTRL                 0x1C
#define MAC_FLOW_CNTRL_BUSY         (1<<0)
#define MAC_FLOW_CNTRL_ENABLE       (1<<1)
#define MAC_PASS_CONTROL            (1<<2)
#define MAC_SET_PAUSE(X)        (((X)&0xffff)<<16)
#define MAC_VLAN1_TAG                  0x20
#define MAC_VLAN2_TAG                  0x24

/* Ethernet Controller Enable */
#define AU1000_MAC0_ENABLE       0xB0520000
#define AU1000_MAC1_ENABLE       0xB0520004
#define AU1500_MAC0_ENABLE       0xB1520000
#define AU1500_MAC1_ENABLE       0xB1520004
#define AU1100_MAC0_ENABLE       0xB0520000
#define AU1550_MAC0_ENABLE       0xB0520000
#define AU1550_MAC1_ENABLE       0xB0520004

#define MAC_EN_CLOCK_ENABLE         (1<<0)
#define MAC_EN_RESET0               (1<<1)
#define MAC_EN_TOSS                 (0<<2)
#define MAC_EN_CACHEABLE            (1<<3)
#define MAC_EN_RESET1               (1<<4)
#define MAC_EN_RESET2               (1<<5)
#define MAC_DMA_RESET               (1<<6)

/* Ethernet Controller DMA Channels */

#define MAC0_TX_DMA_ADDR         0xB4004000
#define MAC1_TX_DMA_ADDR         0xB4004200
/* offsets from MAC_TX_RING_ADDR address */
#define MAC_TX_BUFF0_STATUS             0x0
#define TX_FRAME_ABORTED            (1<<0)
#define TX_JAB_TIMEOUT              (1<<1)
#define TX_NO_CARRIER               (1<<2)
#define TX_LOSS_CARRIER             (1<<3)
#define TX_EXC_DEF                  (1<<4)
#define TX_LATE_COLL_ABORT          (1<<5)
#define TX_EXC_COLL                 (1<<6)
#define TX_UNDERRUN                 (1<<7)
#define TX_DEFERRED                 (1<<8)
#define TX_LATE_COLL                (1<<9)
#define TX_COLL_CNT_MASK         (0xF<<10)
#define TX_PKT_RETRY               (1<<31)
#define MAC_TX_BUFF0_ADDR                0x4
#define TX_DMA_ENABLE               (1<<0)
#define TX_T_DONE                   (1<<1)
#define TX_GET_DMA_BUFFER(X)    (((X)>>2)&0x3)
#define MAC_TX_BUFF0_LEN                 0x8
#define MAC_TX_BUFF1_STATUS             0x10
#define MAC_TX_BUFF1_ADDR               0x14
#define MAC_TX_BUFF1_LEN                0x18
#define MAC_TX_BUFF2_STATUS             0x20
#define MAC_TX_BUFF2_ADDR               0x24
#define MAC_TX_BUFF2_LEN                0x28
#define MAC_TX_BUFF3_STATUS             0x30
#define MAC_TX_BUFF3_ADDR               0x34
#define MAC_TX_BUFF3_LEN                0x38

#define MAC0_RX_DMA_ADDR         0xB4004100
#define MAC1_RX_DMA_ADDR         0xB4004300
/* offsets from MAC_RX_RING_ADDR */
#define MAC_RX_BUFF0_STATUS              0x0
#define RX_FRAME_LEN_MASK           0x3fff
#define RX_WDOG_TIMER              (1<<14)
#define RX_RUNT                    (1<<15)
#define RX_OVERLEN                 (1<<16)
#define RX_COLL                    (1<<17)
#define RX_ETHER                   (1<<18)
#define RX_MII_ERROR               (1<<19)
#define RX_DRIBBLING               (1<<20)
#define RX_CRC_ERROR               (1<<21)
#define RX_VLAN1                   (1<<22)
#define RX_VLAN2                   (1<<23)
#define RX_LEN_ERROR               (1<<24)
#define RX_CNTRL_FRAME             (1<<25)
#define RX_U_CNTRL_FRAME           (1<<26)
#define RX_MCAST_FRAME             (1<<27)
#define RX_BCAST_FRAME             (1<<28)
#define RX_FILTER_FAIL             (1<<29)
#define RX_PACKET_FILTER           (1<<30)
#define RX_MISSED_FRAME            (1<<31)

#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN |  \
		    RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
		    RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
#define MAC_RX_BUFF0_ADDR                0x4
#define RX_DMA_ENABLE               (1<<0)
#define RX_T_DONE                   (1<<1)
#define RX_GET_DMA_BUFFER(X)    (((X)>>2)&0x3)
#define RX_SET_BUFF_ADDR(X)     ((X)&0xffffffc0)
#define MAC_RX_BUFF1_STATUS              0x10
#define MAC_RX_BUFF1_ADDR                0x14
#define MAC_RX_BUFF2_STATUS              0x20
#define MAC_RX_BUFF2_ADDR                0x24
#define MAC_RX_BUFF3_STATUS              0x30
#define MAC_RX_BUFF3_ADDR                0x34


/* UARTS 0-3 */
#define UART0_ADDR                0xB1100000
#define UART1_ADDR                0xB1200000
#define UART2_ADDR                0xB1300000
#define UART3_ADDR                0xB1400000
#define UART_BASE                 UART0_ADDR
#define UART_DEBUG_BASE           UART2_ADDR

#define UART_RX		0	/* Receive buffer */
#define UART_TX		4	/* Transmit buffer */
#define UART_IER	8	/* Interrupt Enable Register */
#define UART_IIR	0xC	/* Interrupt ID Register */
#define UART_FCR	0x10	/* FIFO Control Register */
#define UART_LCR	0x14	/* Line Control Register */
#define UART_MCR	0x18	/* Modem Control Register */
#define UART_LSR	0x1C	/* Line Status Register */
#define UART_MSR	0x20	/* Modem Status Register */
#define UART_CLK	0x28	/* Baud Rate Clock Divider */
#define UART_ENABLE	0x100	/* Uart enable */

#define UART_EN_CE      1       /* Clock enable */
#define UART_EN_E       2       /* Enable */

#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
#define UART_FCR_TRIGGER_MASK	0xF0 /* Mask for the FIFO trigger range */
#define UART_FCR_R_TRIGGER_1	0x00 /* Mask for receive trigger set at 1 */
#define UART_FCR_R_TRIGGER_4	0x40 /* Mask for receive trigger set at 4 */
#define UART_FCR_R_TRIGGER_8	0x80 /* Mask for receive trigger set at 8 */
#define UART_FCR_R_TRIGGER_14   0xA0 /* Mask for receive trigger set at 14 */
#define UART_FCR_T_TRIGGER_0	0x00 /* Mask for transmit trigger set at 0 */
#define UART_FCR_T_TRIGGER_4	0x10 /* Mask for transmit trigger set at 4 */
#define UART_FCR_T_TRIGGER_8    0x20 /* Mask for transmit trigger set at 8 */
#define UART_FCR_T_TRIGGER_12	0x30 /* Mask for transmit trigger set at 12 */

/*
 * These are the definitions for the Line Control Register
 */
#define UART_LCR_SBC	0x40	/* Set break control */
#define UART_LCR_SPAR	0x20	/* Stick parity (?) */
#define UART_LCR_EPAR	0x10	/* Even parity select */
#define UART_LCR_PARITY	0x08	/* Parity Enable */
#define UART_LCR_STOP	0x04	/* Stop bits: 0=1 stop bit, 1= 2 stop bits */
#define UART_LCR_WLEN5  0x00	/* Wordlength: 5 bits */
#define UART_LCR_WLEN6  0x01	/* Wordlength: 6 bits */
#define UART_LCR_WLEN7  0x02	/* Wordlength: 7 bits */
#define UART_LCR_WLEN8  0x03	/* Wordlength: 8 bits */

/*
 * These are the definitions for the Line Status Register
 */
#define UART_LSR_TEMT	0x40	/* Transmitter empty */
#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
#define UART_LSR_BI	0x10	/* Break interrupt indicator */
#define UART_LSR_FE	0x08	/* Frame error indicator */
#define UART_LSR_PE	0x04	/* Parity error indicator */
#define UART_LSR_OE	0x02	/* Overrun error indicator */
#define UART_LSR_DR	0x01	/* Receiver data ready */

/*
 * These are the definitions for the Interrupt Identification Register
 */
#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
#define UART_IIR_MSI	0x00	/* Modem status interrupt */
#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */

/*
 * These are the definitions for the Interrupt Enable Register
 */
#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */

/*
 * These are the definitions for the Modem Control Register
 */
#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
#define UART_MCR_OUT2	0x08	/* Out2 complement */
#define UART_MCR_OUT1	0x04	/* Out1 complement */
#define UART_MCR_RTS	0x02	/* RTS complement */
#define UART_MCR_DTR	0x01	/* DTR complement */

/*