s3c2440.h

嵌入式试验箱S3C2410的bootloader源代码

#define oINTMSK			0x08
#define oPRIORITY		0x0a
#define oINTPND			0x10
#define oINTOFFSET		0x14
#define oSUBSRCPND		0x18
#define oINTSUBMSK		0x1C
/* Registers */
#define SRCPND			bINT_CTL(oSRCPND)
#define INTMOD			bINT_CTL(oINTMOD)
#define INTMSK			bINT_CTL(oINTMSK)
#define PRIORITY		bINT_CTL(oPRIORITY)
#define INTPND			bINT_CTL(oINTPND)
#define INTOFFSET		bINT_CTL(oINTOFFSET)
#define SUBSRCPND		bINT_CTL(oSUBSRCPND)
#define INTSUBMSK		bINT_CTL(oINTSUBMSK)

#define INT_ADCTC		(1 << 31)	/* ADC EOC interrupt */
#define INT_RTC			(1 << 30)	/* RTC alarm interrupt */
#define INT_SPI1		(1 << 29)	/* UART1 transmit interrupt */
#define INT_UART0		(1 << 28)	/* UART0 transmit interrupt */
#define INT_IIC			(1 << 27)	/* IIC interrupt */
#define INT_USBH		(1 << 26)	/* USB host interrupt */
#define INT_USBD		(1 << 25)	/* USB device interrupt */
#define INT_RESERVED24		(1 << 24)
#define INT_UART1		(1 << 23)	/* UART1 receive interrupt */
#define INT_SPI0		(1 << 22)	/* SPI interrupt */
#define INT_MMC			(1 << 21)	/* MMC interrupt */
#define INT_DMA3		(1 << 20)	/* DMA channel 3 interrupt */
#define INT_DMA2		(1 << 19)	/* DMA channel 2 interrupt */
#define INT_DMA1		(1 << 18)	/* DMA channel 1 interrupt */
#define INT_DMA0		(1 << 17)	/* DMA channel 0 interrupt */
#define INT_LCD			(1 << 16)	/* reserved for future use */
#define INT_UART2		(1 << 15)	/* UART 2 interrupt  */
#define INT_TIMER4		(1 << 14)	/* Timer 4 interrupt */
#define INT_TIMER3		(1 << 13)	/* Timer 3 interrupt */
#define INT_TIMER2		(1 << 12)	/* Timer 2 interrupt */
#define INT_TIMER1		(1 << 11)	/* Timer 1 interrupt */
#define INT_TIMER0		(1 << 10)	/* Timer 0 interrupt */
#define INT_WDT			(1 << 9)	/* Watch-Dog timer interrupt */
#define INT_TICK		(1 << 8)	/* RTC time tick interrupt  */
#define INT_BAT_FLT		(1 << 7)
#define INT_RESERVED6		(1 << 6)	/* Reserved for future use */
#define INT_EINT8_23		(1 << 5)	/* External interrupt 8 ~ 23 */
#define INT_EINT4_7		(1 << 4)	/* External interrupt 4 ~ 7 */
#define INT_EINT3		(1 << 3)	/* External interrupt 3 */
#define INT_EINT2		(1 << 2)	/* External interrupt 2 */
#define INT_EINT1		(1 << 1)	/* External interrupt 1 */
#define INT_EINT0		(1 << 0)	/* External interrupt 0 */

#define INT_ADC			(1 << 10)
#define INT_TC			(1 << 9)
#define INT_ERR2		(1 << 8)
#define INT_TXD2		(1 << 7)
#define INT_RXD2		(1 << 6)
#define INT_ERR1		(1 << 5)
#define INT_TXD1		(1 << 4)
#define INT_RXD1		(1 << 3)
#define INT_ERR0		(1 << 2)
#define INT_TXD0		(1 << 1)
#define INT_RXD0		(1 << 0)

/* NAND Flash Controller */
#define NAND_CTL_BASE		0x4E000000
#define bINT_CTL(Nb)		__REG(INT_CTL_BASE + (Nb))
/* Offset */
#define oNFCONF			0x00
#define oNFCONT			0x04
#define oNFCMD			0x08
#define oNFADDR			0x0c
#define oNFDATA			0x10
#define oNFSTAT			0x20
#define oNFECC			0x2c


/* PWM Timer */
#define bPWM_TIMER(Nb)          __REG(0x51000000 + (Nb))
#define bPWM_BUFn(Nb,x)         bPWM_TIMER(0x0c + (Nb)*0x0c + (x))
/* Registers */
#define TCFG0                   bPWM_TIMER(0x00)
#define TCFG1                   bPWM_TIMER(0x04)
#define TCON                    bPWM_TIMER(0x08)
#define TCNTB0                  bPWM_BUFn(0,0x0)
#define TCMPB0                  bPWM_BUFn(0,0x4)
#define TCNTO0                  bPWM_BUFn(0,0x8)
#define TCNTB1                  bPWM_BUFn(1,0x0)
#define TCMPB1                  bPWM_BUFn(1,0x4)
#define TCNTO1                  bPWM_BUFn(1,0x8)
#define TCNTB2                  bPWM_BUFn(2,0x0)
#define TCMPB2                  bPWM_BUFn(2,0x4)
#define TCNTO2                  bPWM_BUFn(2,0x8)
#define TCNTB3                  bPWM_BUFn(3,0x0)
#define TCMPB3                  bPWM_BUFn(3,0x4)
#define TCNTO3                  bPWM_BUFn(3,0x8)
#define TCNTB4                  bPWM_BUFn(4,0x0)
#define TCNTO4                  bPWM_BUFn(4,0x4)
/* Fields */
#define fTCFG0_DZONE            Fld(8,16)       /* the dead zone length (= timer 0) */
#define fTCFG0_PRE1             Fld(8,8)        /* prescaler value for time 2,3,4 */
#define fTCFG0_PRE0             Fld(8,0)        /* prescaler value for time 0,1 */
#define fTCFG1_MUX4		Fld(4,16)
/* bits */
#define TCFG0_DZONE(x)          FInsrt((x), fTCFG0_DZONE)
#define TCFG0_PRE1(x)           FInsrt((x), fTCFG0_PRE1)
#define TCFG0_PRE0(x)           FInsrt((x), fTCFG0_PRE0)
#define TCON_4_AUTO             (1 << 22)       /* auto reload on/off for Timer 4 */
#define TCON_4_UPDATE           (1 << 21)       /* manual Update TCNTB4 */
#define TCON_4_ONOFF            (1 << 20)       /* 0: Stop, 1: start Timer 4 */
#define COUNT_4_ON              (TCON_4_ONOFF*1)
#define COUNT_4_OFF             (TCON_4_ONOFF*0)
#define TCON_3_AUTO     (1 << 19)       /* auto reload on/off for Timer 3 */
#define TIMER3_ATLOAD_ON        (TCON_3_AUTO*1)
#define TIMER3_ATLAOD_OFF       FClrBit(TCON, TCON_3_AUTO)
#define TCON_3_INVERT   (1 << 18)       /* 1: Inverter on for TOUT3 */
#define TIMER3_IVT_ON   (TCON_3_INVERT*1)
#define TIMER3_IVT_OFF  (FClrBit(TCON, TCON_3_INVERT))
#define TCON_3_MAN      (1 << 17)       /* manual Update TCNTB3,TCMPB3 */
#define TIMER3_MANUP    (TCON_3_MAN*1)
#define TIMER3_NOP      (FClrBit(TCON, TCON_3_MAN))
#define TCON_3_ONOFF    (1 << 16)       /* 0: Stop, 1: start Timer 3 */
#define TIMER3_ON       (TCON_3_ONOFF*1)
#define TIMER3_OFF      (FClrBit(TCON, TCON_3_ONOFF))
/* macros */
#define GET_PRESCALE_TIMER4(x)	FExtr((x), fTCFG0_PRE1)
#define GET_DIVIDER_TIMER4(x)	FExtr((x), fTCFG1_MUX4)

/*
 * NAND Flash Controller (Page 6-1 ~ 6-8)
 *
 * Register
   NFCONF   NAND Flash Configuration    [word, R/W, 0x00000000]
   NFCMD    NAND Flash Command Set      [word, R/W, 0x00000000]
   NFADDR   NAND Flash Address Set      [word, R/W, 0x00000000]
   NFDATA   NAND Flash Data             [word, R/W, 0x00000000]
   NFSTAT   NAND Flash Status           [word, R, 0x00000000]
   NFECC    NAND Flash ECC              [3 bytes, R, 0x00000000]
 *
 */
#define bNAND_CTL(Nb)   __REG(0x4e000000 + (Nb))
#define NFCONF          bNAND_CTL(0x00)
#define NFCONT          bNAND_CTL(0x04)
#define NFCMD       bNAND_CTL(0x08)
#define NFADDR      bNAND_CTL(0x0c)
#define NFDATA      __REGb(0x4e000000 + (0x10))
#define NFSTAT      bNAND_CTL(0x20)
#define NFECC       bNAND_CTL(0x2c)

#define fNFCONF_TWRPH1   Fld(3,4)
#define NFCONF_TWRPH1    FMsk(fNFCONF_TWRPH1)
#define NFCONF_TWRPH1_7  FInsrt(0x7, fNFCONF_TWRPH1) /* 7 */
#define fNFCONF_TWRPH0   Fld(3,8)
#define NFCONF_TWRPH0    FMsk(fNFCONF_TWRPH0)
#define NFCONF_TWRPH0_7  FInsrt(0x7, fNFCONF_TWRPH0) /* 7 */
#define fNFCONF_TACLS    Fld(3,12)
#define NFCONF_TACLS     FMsk(fNFCONF_TACLS)
#define NFCONF_TACLS_7   FInsrt(0x7, fNFCONF_TACLS) /* 7 */
#define fNFCONT_nFCE     Fld(1,1)
#define NFCONT_nFCE      FMsk(fNFCONT_nFCE)
#define NFCONT_nFCE_LOW  FInsrt(0x0, fNFCONT_nFCE) /* active */
#define NFCONT_nFCE_HIGH FInsrt(0x1, fNFCONT_nFCE) /* inactive */

#define fNFCONT_ECC      Fld(1,4)
#define NFCONT_ECC       FMsk(fNFCONT_ECC)
#define NFCONT_ECC_NINIT FInsrt(0x0, fNFCONT_ECC) /* not initialize */
#define NFCONT_ECC_INIT  FInsrt(0x1, fNFCONT_ECC)    /* initialize */

#define fNFCONT_MAINECC  Fld(1,5)
#define NFCONT_MAINECC       FMsk(fNFCONT_MAINECC)
#define NFCONT_MAINECC_UNLOCK FInsrt(0x0, fNFCONT_MAINECC) 
#define NFCONT_MAINECC_LOCK   FInsrt(0x1, fNFCONT_MAINECC)

#define fNFCONF_ADDRSTEP Fld(1,13)                 /* Addressing Step */
#define NFCONF_ADDRSTEP  FMsk(fNFCONF_ADDRSTEP)

/* S3C2440 H/W Set */
#define fNFCONF_PAGESIZE Fld(1,2)
#define NFCONF_PAGESIZE  FMsk(fNFCONF_PAGESIZE)
#define NFCONF_PAGESIZE_256  FInsrt(0x0, fNFCONF_PAGESIZE) /* 256 bytes */
#define NFCONF_PAGESIZE_512  FInsrt(0x1, fNFCONF_PAGESIZE) /* 512 bytes */

#define fNFCONT_FCTRL    Fld(1,0)  /* Flash controller enable/disable */
#define NFCONT_FCTRL     FMsk(fNFCONT_FCTRL)
#define NFCONT_FCTRL_DIS FInsrt(0x0, fNFCONT_FCTRL) /* Disable */
#define NFCONT_FCTRL_EN  FInsrt(0x1, fNFCONT_FCTRL) /* Enable */

#define NFSTAT_RnB      (1 << 2)


/*
 * Power Management
 */
#define SPI_CLK		(1 << 18)
#define IIS_CLK		(1 << 17)
#define IIC_CLK		(1 << 16
#define ADC_CLK		(1 << 15)
#define RTC_CLK		(1 << 14)
#define GPIO_CLK	(1 << 13)
#define UART2_CLK	(1 << 12)
#define UART1_CLK	(1 << 11)
#define UART0_CLK	(1 << 10)
#define SDI_CLK		(1 << 9)
#define PWM_CLK		(1 << 8)
#define USBSLAVE_CLK	(1 << 7)
#define USBHOST_CLK	(1 << 6)
#define LCDC_CLK	(1 << 5)
#define NANDCTL_CLK	(1 << 4)
#define SLEEP_ON	(1 << 3)
#define IDLE		(1 << 2)

#define GSTATUS(Nb)	__REG(0x560000AC + (Nb*4))
#define GSTATUS0	GSTATUS(0)
#define GSTATUS1	GSTATUS(1)
#define GSTATUS2	GSTATUS(2)
#define GSTATUS3	GSTATUS(3)
#define GSTATUS4	GSTATUS(4)
#define PMST		GSTATUS2
#define PMSR0		GSTATUS3
#define PMSR1		GSTATUS4
#define PMCTL0		CLKCON
#define PMCTL1		MISCCR
#define SCLKE		(1 << 19)
#define SCLK1		(1 << 18)
#define SCLK0		(1 << 17)
#define USBSPD1		(1 << 13)
#define USBSPD0		(1 << 12)
#define PMST_HWR	(1 << 0)
#define PMST_SMR	(1 << 1)
#define PMST_WDR	(1 << 2)


#define HIDDEN(Nb)	__REG(0x560000C0 + (Nb*4))
#define FLTOUT		HIDDEN(0)
#define DSC0		HIDDEN(1)
#define DSC1		HIDDEN(2)
#define MSLCON		HIDDEN(3)