📄 system_stm32f10x.lst
字号:
70 0036 0193 str r3, [sp, #4]
71 .LVL0:
72 0038 0093 str r3, [sp, #0]
73 .LVL1:
680:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
681:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
682:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Enable HSE */
683:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CR |= ((uint32_t)RCC_CR_HSEON);
74 .loc 1 683 0
75 003a 1368 ldr r3, [r2, #0]
76 003c 43F48033 orr r3, r3, #65536
77 0040 1360 str r3, [r2, #0]
78 .LVL2:
79 .L3:
684:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
685:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Wait till HSE is ready and if Time out is reached exit */
686:lib/CMSIS/Core/CM3/system_stm32f10x.c **** do
687:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
688:lib/CMSIS/Core/CM3/system_stm32f10x.c **** HSEStatus = RCC->CR & RCC_CR_HSERDY;
80 .loc 1 688 0
81 0042 294B ldr r3, .L13
82 0044 1B68 ldr r3, [r3, #0]
83 0046 03F40033 and r3, r3, #131072
84 004a 0093 str r3, [sp, #0]
85 .LVL3:
689:lib/CMSIS/Core/CM3/system_stm32f10x.c **** StartUpCounter++;
86 .loc 1 689 0
87 004c 019B ldr r3, [sp, #4]
88 004e 0133 adds r3, r3, #1
89 0050 0193 str r3, [sp, #4]
90 .LVL4:
690:lib/CMSIS/Core/CM3/system_stm32f10x.c **** } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
91 .loc 1 690 0
92 0052 009B ldr r3, [sp, #0]
93 0054 1BB9 cbnz r3, .L2
94 .LVL5:
95 0056 019B ldr r3, [sp, #4]
96 0058 B3F5A06F cmp r3, #1280
97 005c F1D1 bne .L3
98 .L2:
691:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
692:lib/CMSIS/Core/CM3/system_stm32f10x.c **** if ((RCC->CR & RCC_CR_HSERDY) != RESET)
99 .loc 1 692 0
100 005e 224B ldr r3, .L13
101 0060 1B68 ldr r3, [r3, #0]
102 0062 13F40033 ands r3, r3, #131072
693:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
694:lib/CMSIS/Core/CM3/system_stm32f10x.c **** HSEStatus = (uint32_t)0x01;
103 .loc 1 694 0
104 0066 18BF it ne
105 0068 0123 movne r3, #1
695:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
696:lib/CMSIS/Core/CM3/system_stm32f10x.c **** else
697:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
698:lib/CMSIS/Core/CM3/system_stm32f10x.c **** HSEStatus = (uint32_t)0x00;
106 .loc 1 698 0
107 006a 0093 str r3, [sp, #0]
108 .LVL6:
699:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
700:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
701:lib/CMSIS/Core/CM3/system_stm32f10x.c **** if (HSEStatus == (uint32_t)0x01)
109 .loc 1 701 0
110 006c 009B ldr r3, [sp, #0]
111 006e 012B cmp r3, #1
112 0070 36D1 bne .L6
113 .LVL7:
702:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
703:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Enable Prefetch Buffer */
704:lib/CMSIS/Core/CM3/system_stm32f10x.c **** FLASH->ACR |= FLASH_ACR_PRFTBE;
114 .loc 1 704 0
115 0072 1F4A ldr r2, .L13+8
116 0074 1368 ldr r3, [r2, #0]
117 0076 43F01003 orr r3, r3, #16
118 007a 1360 str r3, [r2, #0]
705:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
706:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Flash 2 wait state */
707:lib/CMSIS/Core/CM3/system_stm32f10x.c **** FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
119 .loc 1 707 0
120 007c 1368 ldr r3, [r2, #0]
121 007e 23F00303 bic r3, r3, #3
122 0082 1360 str r3, [r2, #0]
708:lib/CMSIS/Core/CM3/system_stm32f10x.c **** FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
123 .loc 1 708 0
124 0084 1368 ldr r3, [r2, #0]
125 0086 43F00203 orr r3, r3, #2
126 008a 1360 str r3, [r2, #0]
709:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
710:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< HCLK = SYSCLK */
711:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
127 .loc 1 711 0
128 008c A2F58052 sub r2, r2, #4096
129 0090 5368 ldr r3, [r2, #4]
130 0092 5360 str r3, [r2, #4]
712:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
713:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< PCLK2 = HCLK */
714:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
131 .loc 1 714 0
132 0094 5368 ldr r3, [r2, #4]
133 0096 5360 str r3, [r2, #4]
715:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
716:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< PCLK1 = HCLK */
717:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
134 .loc 1 717 0
135 0098 5368 ldr r3, [r2, #4]
136 009a 43F48063 orr r3, r3, #1024
137 009e 5360 str r3, [r2, #4]
718:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
719:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< PLLCLK = 8MHz * 9 = 72 MHz */
720:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
138 .loc 1 720 0
139 00a0 5368 ldr r3, [r2, #4]
140 00a2 23F47C13 bic r3, r3, #4128768
141 00a6 5360 str r3, [r2, #4]
721:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL9);
142 .loc 1 721 0
143 00a8 5368 ldr r3, [r2, #4]
144 00aa 43F4E813 orr r3, r3, #1900544
145 00ae 5360 str r3, [r2, #4]
722:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
723:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Enable PLL */
724:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CR |= RCC_CR_PLLON;
146 .loc 1 724 0
147 00b0 1368 ldr r3, [r2, #0]
148 00b2 43F08073 orr r3, r3, #16777216
149 00b6 1360 str r3, [r2, #0]
150 .L7:
725:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
726:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Wait till PLL is ready */
727:lib/CMSIS/Core/CM3/system_stm32f10x.c **** while((RCC->CR & RCC_CR_PLLRDY) == 0)
151 .loc 1 727 0
152 00b8 0B4A ldr r2, .L13
153 00ba 1368 ldr r3, [r2, #0]
154 00bc 13F0007F tst r3, #33554432
155 00c0 FAD0 beq .L7
728:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
729:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
730:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
731:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Select PLL as system clock source */
732:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
156 .loc 1 732 0
157 00c2 5368 ldr r3, [r2, #4]
158 00c4 23F00303 bic r3, r3, #3
159 00c8 5360 str r3, [r2, #4]
733:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
160 .loc 1 733 0
161 00ca 5368 ldr r3, [r2, #4]
162 00cc 43F00203 orr r3, r3, #2
163 00d0 5360 str r3, [r2, #4]
164 .L8:
734:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
735:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Wait till PLL is used as system clock source */
736:lib/CMSIS/Core/CM3/system_stm32f10x.c **** while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
165 .loc 1 736 0
166 00d2 054B ldr r3, .L13
167 00d4 5B68 ldr r3, [r3, #4]
168 00d6 03F00C03 and r3, r3, #12
169 00da 082B cmp r3, #8
170 00dc F9D1 bne .L8
171 00de 00E0 b .L12
172 .L6:
173 00e0 FEE7 b .L6
174 .L12:
175 .LBE9:
176 .LBE8:
177 .LBE7:
178 .LBE6:
179 .loc 1 181 0
180 00e2 02B0 add sp, sp, #8
181 00e4 7047 bx lr
182 .L14:
183 00e6 C046 .align 2
184 .L13:
185 00e8 00100240 .word 1073876992
186 00ec 0000FFF8 .word -117506048
187 00f0 00200240 .word 1073881088
188 .LFE26:
190 .global SystemFrequency
191 .global SystemFrequency_SysClk
192 .global SystemFrequency_AHBClk
193 .global SystemFrequency_APB1Clk
194 .global SystemFrequency_APB2Clk
195 .section .rodata.SystemFrequency_AHBClk,"a",%progbi⌨️ 快捷键说明
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