📄 system_stm32f10x.lst
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496:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Go to infinite loop */
497:lib/CMSIS/Core/CM3/system_stm32f10x.c **** while (1)
498:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
499:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
500:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
501:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
502:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #elif defined SYSCLK_FREQ_48MHz
503:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /**
504:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
505:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * and PCLK1 prescalers.
506:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @param None.
507:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @arg None.
508:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @note : This function should be used only after reset.
509:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @retval value: None.
510:lib/CMSIS/Core/CM3/system_stm32f10x.c **** */
511:lib/CMSIS/Core/CM3/system_stm32f10x.c **** static void SetSysClockTo48(void)
512:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
513:lib/CMSIS/Core/CM3/system_stm32f10x.c **** __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
514:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
515:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
516:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Enable HSE */
517:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CR |= ((uint32_t)RCC_CR_HSEON);
518:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
519:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Wait till HSE is ready and if Time out is reached exit */
520:lib/CMSIS/Core/CM3/system_stm32f10x.c **** do
521:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
522:lib/CMSIS/Core/CM3/system_stm32f10x.c **** HSEStatus = RCC->CR & RCC_CR_HSERDY;
523:lib/CMSIS/Core/CM3/system_stm32f10x.c **** StartUpCounter++;
524:lib/CMSIS/Core/CM3/system_stm32f10x.c **** } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
525:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
526:lib/CMSIS/Core/CM3/system_stm32f10x.c **** if ((RCC->CR & RCC_CR_HSERDY) != RESET)
527:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
528:lib/CMSIS/Core/CM3/system_stm32f10x.c **** HSEStatus = (uint32_t)0x01;
529:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
530:lib/CMSIS/Core/CM3/system_stm32f10x.c **** else
531:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
532:lib/CMSIS/Core/CM3/system_stm32f10x.c **** HSEStatus = (uint32_t)0x00;
533:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
534:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
535:lib/CMSIS/Core/CM3/system_stm32f10x.c **** if (HSEStatus == (uint32_t)0x01)
536:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
537:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Enable Prefetch Buffer */
538:lib/CMSIS/Core/CM3/system_stm32f10x.c **** FLASH->ACR |= FLASH_ACR_PRFTBE;
539:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
540:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Flash 1 wait state */
541:lib/CMSIS/Core/CM3/system_stm32f10x.c **** FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
542:lib/CMSIS/Core/CM3/system_stm32f10x.c **** FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
543:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
544:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< HCLK = SYSCLK */
545:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
546:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
547:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< PCLK2 = HCLK */
548:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
549:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
550:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< PCLK1 = HCLK */
551:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
552:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
553:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< PLLCLK = 8MHz * 6 = 48 MHz */
554:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
555:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL6);
556:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
557:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Enable PLL */
558:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CR |= RCC_CR_PLLON;
559:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
560:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Wait till PLL is ready */
561:lib/CMSIS/Core/CM3/system_stm32f10x.c **** while((RCC->CR & RCC_CR_PLLRDY) == 0)
562:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
563:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
564:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
565:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Select PLL as system clock source */
566:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
567:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
568:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
569:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Wait till PLL is used as system clock source */
570:lib/CMSIS/Core/CM3/system_stm32f10x.c **** while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
571:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
572:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
573:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
574:lib/CMSIS/Core/CM3/system_stm32f10x.c **** else
575:lib/CMSIS/Core/CM3/system_stm32f10x.c **** { /*!< If HSE fails to start-up, the application will have wrong clock
576:lib/CMSIS/Core/CM3/system_stm32f10x.c **** configuration. User can add here some code to deal with this error */
577:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
578:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Go to infinite loop */
579:lib/CMSIS/Core/CM3/system_stm32f10x.c **** while (1)
580:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
581:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
582:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
583:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
584:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
585:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #elif defined SYSCLK_FREQ_56MHz
586:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /**
587:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
588:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * and PCLK1 prescalers.
589:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @param None.
590:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @arg None.
591:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @note : This function should be used only after reset.
592:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @retval value: None.
593:lib/CMSIS/Core/CM3/system_stm32f10x.c **** */
594:lib/CMSIS/Core/CM3/system_stm32f10x.c **** static void SetSysClockTo56(void)
595:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
596:lib/CMSIS/Core/CM3/system_stm32f10x.c **** __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
597:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
598:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
599:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Enable HSE */
600:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CR |= ((uint32_t)RCC_CR_HSEON);
601:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
602:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Wait till HSE is ready and if Time out is reached exit */
603:lib/CMSIS/Core/CM3/system_stm32f10x.c **** do
604:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
605:lib/CMSIS/Core/CM3/system_stm32f10x.c **** HSEStatus = RCC->CR & RCC_CR_HSERDY;
606:lib/CMSIS/Core/CM3/system_stm32f10x.c **** StartUpCounter++;
607:lib/CMSIS/Core/CM3/system_stm32f10x.c **** } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
608:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
609:lib/CMSIS/Core/CM3/system_stm32f10x.c **** if ((RCC->CR & RCC_CR_HSERDY) != RESET)
610:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
611:lib/CMSIS/Core/CM3/system_stm32f10x.c **** HSEStatus = (uint32_t)0x01;
612:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
613:lib/CMSIS/Core/CM3/system_stm32f10x.c **** else
614:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
615:lib/CMSIS/Core/CM3/system_stm32f10x.c **** HSEStatus = (uint32_t)0x00;
616:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
617:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
618:lib/CMSIS/Core/CM3/system_stm32f10x.c **** if (HSEStatus == (uint32_t)0x01)
619:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
620:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Enable Prefetch Buffer */
621:lib/CMSIS/Core/CM3/system_stm32f10x.c **** FLASH->ACR |= FLASH_ACR_PRFTBE;
622:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
623:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Flash 1 wait state */
624:lib/CMSIS/Core/CM3/system_stm32f10x.c **** FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
625:lib/CMSIS/Core/CM3/system_stm32f10x.c **** FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
626:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
627:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< HCLK = SYSCLK */
628:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
629:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
630:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< PCLK2 = HCLK */
631:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
632:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
633:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< PCLK1 = HCLK */
634:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
635:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
636:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< PLLCLK = 8MHz * 7 = 56 MHz */
637:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
638:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL7);
639:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
640:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Enable PLL */
641:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CR |= RCC_CR_PLLON;
642:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
643:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Wait till PLL is ready */
644:lib/CMSIS/Core/CM3/system_stm32f10x.c **** while((RCC->CR & RCC_CR_PLLRDY) == 0)
645:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
646:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
647:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
648:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Select PLL as system clock source */
649:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
650:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
651:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
652:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Wait till PLL is used as system clock source */
653:lib/CMSIS/Core/CM3/system_stm32f10x.c **** while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
654:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
655:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
656:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
657:lib/CMSIS/Core/CM3/system_stm32f10x.c **** else
658:lib/CMSIS/Core/CM3/system_stm32f10x.c **** { /*!< If HSE fails to start-up, the application will have wrong clock
659:lib/CMSIS/Core/CM3/system_stm32f10x.c **** configuration. User can add here some code to deal with this error */
660:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
661:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Go to infinite loop */
662:lib/CMSIS/Core/CM3/system_stm32f10x.c **** while (1)
663:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
664:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
665:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
666:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
667:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
668:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #elif defined SYSCLK_FREQ_72MHz
669:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /**
670:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
671:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * and PCLK1 prescalers.
672:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @param None.
673:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @arg None.
674:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @note : This function should be used only after reset.
675:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @retval value: None.
676:lib/CMSIS/Core/CM3/system_stm32f10x.c **** */
677:lib/CMSIS/Core/CM3/system_stm32f10x.c **** static void SetSysClockTo72(void)
678:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
679:lib/CMSIS/Core/CM3/system_stm32f10x.c **** __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
69 .loc 1 679 0
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