system_stm32f10x.lst

STM32 "kickstart" program with newlib/stdio like sprintf&printf

 311:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
 312:lib/CMSIS/Core/CM3/system_stm32f10x.c ****       
 313:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< PCLK2 = HCLK */
 314:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
 315:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     
 316:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< PCLK1 = HCLK */
 317:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
 318:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     
 319:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Select HSE as system clock source */
 320:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 321:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
 322:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 323:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Wait till HSE is used as system clock source */
 324:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
 325:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     {
 326:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     }
 327:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   }
 328:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   else
 329:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   { /*!< If HSE fails to start-up, the application will have wrong clock 
 330:lib/CMSIS/Core/CM3/system_stm32f10x.c ****          configuration. User can add here some code to deal with this error */    
 331:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 332:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Go to infinite loop */
 333:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     while (1)
 334:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     {
 335:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     }
 336:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   }  
 337:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
 338:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #elif defined SYSCLK_FREQ_20MHz
 339:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /**
 340:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   * @brief Sets System clock frequency to 20MHz and configure HCLK, PCLK2 
 341:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   *        and PCLK1 prescalers.
 342:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   * @param None.
 343:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   * @arg None.
 344:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   * @note : This function should be used only after reset.
 345:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   * @retval value: None.
 346:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   */
 347:lib/CMSIS/Core/CM3/system_stm32f10x.c **** static void SetSysClockTo20(void)
 348:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
 349:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 350:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   
 351:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   /*!< SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
 352:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   /*!< Enable HSE */    
 353:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 354:lib/CMSIS/Core/CM3/system_stm32f10x.c ****  
 355:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   /*!< Wait till HSE is ready and if Time out is reached exit */
 356:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   do
 357:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   {
 358:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     HSEStatus = RCC->CR & RCC_CR_HSERDY;
 359:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     StartUpCounter++;  
 360:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
 361:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 362:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
 363:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   {
 364:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     HSEStatus = (uint32_t)0x01;
 365:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   }
 366:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   else
 367:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   {
 368:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     HSEStatus = (uint32_t)0x00;
 369:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   }  
 370:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 371:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   if (HSEStatus == (uint32_t)0x01)
 372:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   {
 373:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Enable Prefetch Buffer */
 374:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     FLASH->ACR |= FLASH_ACR_PRFTBE;
 375:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 376:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Flash 0 wait state */
 377:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
 378:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
 379:lib/CMSIS/Core/CM3/system_stm32f10x.c ****  
 380:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< HCLK = SYSCLK */
 381:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
 382:lib/CMSIS/Core/CM3/system_stm32f10x.c ****       
 383:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< PCLK2 = HCLK */
 384:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
 385:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     
 386:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< PCLK1 = HCLK */
 387:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
 388:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     
 389:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< PLLCLK = (8MHz / 2) * 5 = 20 MHz */
 390:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
 391:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL5);
 392:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 393:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Enable PLL */
 394:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CR |= RCC_CR_PLLON;
 395:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 396:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Wait till PLL is ready */
 397:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     while((RCC->CR & RCC_CR_PLLRDY) == 0)
 398:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     {
 399:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     }
 400:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 401:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Select PLL as system clock source */
 402:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 403:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
 404:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 405:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Wait till PLL is used as system clock source */
 406:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
 407:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     {
 408:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     }
 409:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   }
 410:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   else
 411:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   { /*!< If HSE fails to start-up, the application will have wrong clock 
 412:lib/CMSIS/Core/CM3/system_stm32f10x.c ****          configuration. User can add here some code to deal with this error */    
 413:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 414:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Go to infinite loop */
 415:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     while (1)
 416:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     {
 417:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     }
 418:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   } 
 419:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
 420:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #elif defined SYSCLK_FREQ_36MHz
 421:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /**
 422:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
 423:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   *        and PCLK1 prescalers. 
 424:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   * @param None.
 425:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   * @arg None.
 426:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   * @note : This function should be used only after reset.
 427:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   * @retval value: None.
 428:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   */
 429:lib/CMSIS/Core/CM3/system_stm32f10x.c **** static void SetSysClockTo36(void)
 430:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
 431:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 432:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   
 433:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   /*!< SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
 434:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   /*!< Enable HSE */    
 435:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 436:lib/CMSIS/Core/CM3/system_stm32f10x.c ****  
 437:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   /*!< Wait till HSE is ready and if Time out is reached exit */
 438:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   do
 439:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   {
 440:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     HSEStatus = RCC->CR & RCC_CR_HSERDY;
 441:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     StartUpCounter++;  
 442:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
 443:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 444:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
 445:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   {
 446:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     HSEStatus = (uint32_t)0x01;
 447:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   }
 448:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   else
 449:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   {
 450:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     HSEStatus = (uint32_t)0x00;
 451:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   }  
 452:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 453:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   if (HSEStatus == (uint32_t)0x01)
 454:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   {
 455:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Enable Prefetch Buffer */
 456:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     FLASH->ACR |= FLASH_ACR_PRFTBE;
 457:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 458:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Flash 1 wait state */
 459:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
 460:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
 461:lib/CMSIS/Core/CM3/system_stm32f10x.c ****  
 462:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< HCLK = SYSCLK */
 463:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
 464:lib/CMSIS/Core/CM3/system_stm32f10x.c ****       
 465:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< PCLK2 = HCLK */
 466:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
 467:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     
 468:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< PCLK1 = HCLK */
 469:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
 470:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     
 471:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< PLLCLK = (8MHz / 2) * 9 = 36 MHz */
 472:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
 473:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL9);
 474:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 475:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Enable PLL */
 476:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CR |= RCC_CR_PLLON;
 477:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 478:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Wait till PLL is ready */
 479:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     while((RCC->CR & RCC_CR_PLLRDY) == 0)
 480:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     {
 481:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     }
 482:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 483:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Select PLL as system clock source */
 484:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 485:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
 486:lib/CMSIS/Core/CM3/system_stm32f10x.c **** 
 487:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     /*!< Wait till PLL is used as system clock source */
 488:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
 489:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     {
 490:lib/CMSIS/Core/CM3/system_stm32f10x.c ****     }
 491:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   }
 492:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   else
 493:lib/CMSIS/Core/CM3/system_stm32f10x.c ****   { /*!< If HSE fails to start-up, the application will have wrong clock 
 494:lib/CMSIS/Core/CM3/system_stm32f10x.c ****          configuration. User can add here some code to deal with this error */    
 495:lib/CMSIS/Core/CM3/system_stm32f10x.c ****