📄 system_stm32f10x.lst
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32 @ args = 0, pretend = 0, frame = 8
33 @ frame_needed = 0, uses_anonymous_args = 0
34 @ link register save eliminated.
163:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< RCC system reset(for debug purpose) */
164:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Set HSION bit */
165:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CR |= (uint32_t)0x00000001;
35 .loc 1 165 0
36 0000 394A ldr r2, .L13
37 .loc 1 162 0
38 0002 82B0 sub sp, sp, #8
39 .LCFI0:
40 .loc 1 165 0
41 0004 1368 ldr r3, [r2, #0]
42 0006 43F00103 orr r3, r3, #1
43 000a 1360 str r3, [r2, #0]
166:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
167:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR &= (uint32_t)0xF8FF0000;
44 .loc 1 167 0
45 000c 5168 ldr r1, [r2, #4]
46 000e 374B ldr r3, .L13+4
47 0010 01EA0303 and r3, r1, r3
48 0014 5360 str r3, [r2, #4]
168:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Reset HSEON, CSSON and PLLON bits */
169:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CR &= (uint32_t)0xFEF6FFFF;
49 .loc 1 169 0
50 0016 1368 ldr r3, [r2, #0]
51 0018 23F08473 bic r3, r3, #17301504
52 001c 23F48033 bic r3, r3, #65536
53 0020 1360 str r3, [r2, #0]
170:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Reset HSEBYP bit */
171:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CR &= (uint32_t)0xFFFBFFFF;
54 .loc 1 171 0
55 0022 1368 ldr r3, [r2, #0]
56 0024 23F48023 bic r3, r3, #262144
57 0028 1360 str r3, [r2, #0]
172:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
173:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CFGR &= (uint32_t)0xFF80FFFF;
58 .loc 1 173 0
59 002a 5368 ldr r3, [r2, #4]
60 002c 23F4FE03 bic r3, r3, #8323072
61 0030 5360 str r3, [r2, #4]
174:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Disable all interrupts */
175:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CIR = 0x00000000;
62 .loc 1 175 0
63 0032 0023 movs r3, #0
64 0034 9360 str r3, [r2, #8]
65 .LBB6:
66 .LBB7:
67 .LBB8:
68 .LBB9:
176:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
177:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
178:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Configure the Flash Latency cycles and enable prefetch buffer */
179:lib/CMSIS/Core/CM3/system_stm32f10x.c **** SetSysClock();
180:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
181:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
182:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
183:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /**
184:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1
185:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * prescalers.
186:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @param None.
187:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @arg None.
188:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @note : None.
189:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @retval value: None.
190:lib/CMSIS/Core/CM3/system_stm32f10x.c **** */
191:lib/CMSIS/Core/CM3/system_stm32f10x.c **** static void SetSysClock(void)
192:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
193:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #ifdef SYSCLK_FREQ_HSE
194:lib/CMSIS/Core/CM3/system_stm32f10x.c **** SetSysClockToHSE();
195:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #elif defined SYSCLK_FREQ_20MHz
196:lib/CMSIS/Core/CM3/system_stm32f10x.c **** SetSysClockTo20();
197:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #elif defined SYSCLK_FREQ_36MHz
198:lib/CMSIS/Core/CM3/system_stm32f10x.c **** SetSysClockTo36();
199:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #elif defined SYSCLK_FREQ_48MHz
200:lib/CMSIS/Core/CM3/system_stm32f10x.c **** SetSysClockTo48();
201:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #elif defined SYSCLK_FREQ_56MHz
202:lib/CMSIS/Core/CM3/system_stm32f10x.c **** SetSysClockTo56();
203:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #elif defined SYSCLK_FREQ_72MHz
204:lib/CMSIS/Core/CM3/system_stm32f10x.c **** SetSysClockTo72();
205:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #endif
206:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
207:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< If none of the define above is enabled, the HSI is used as System clock
208:lib/CMSIS/Core/CM3/system_stm32f10x.c **** source (default after reset) */
209:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
210:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
211:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /**
212:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @brief Setup the external memory controller. Called in startup_stm32f10x.s
213:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * before jump to __main
214:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @param None.
215:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @arg None.
216:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @note : None.
217:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @retval value: None.
218:lib/CMSIS/Core/CM3/system_stm32f10x.c **** */
219:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #ifdef DATA_IN_ExtSRAM
220:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /**
221:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @brief Setup the external memory controller.
222:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * Called in startup_stm32f10x_xx.s/.c before jump to main.
223:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * This function configures the external SRAM mounted on STM3210E-EVAL
224:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * board (STM32 High density devices). This SRAM will be used as program
225:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * data memory (including heap and stack).
226:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @param None.
227:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @arg None.
228:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @note : None.
229:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @retval value: None.
230:lib/CMSIS/Core/CM3/system_stm32f10x.c **** */
231:lib/CMSIS/Core/CM3/system_stm32f10x.c **** void SystemInit_ExtMemCtl(void)
232:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
233:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
234:lib/CMSIS/Core/CM3/system_stm32f10x.c **** required, then adjust the Register Addresses */
235:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
236:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Enable FSMC clock */
237:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->AHBENR = 0x00000114;
238:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
239:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
240:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->APB2ENR = 0x000001E0;
241:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
242:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
243:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*---------------- SRAM Address lines configuration -------------------------*/
244:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*---------------- NOE and NWE configuration --------------------------------*/
245:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*---------------- NE3 configuration ----------------------------------------*/
246:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*---------------- NBL0, NBL1 configuration ---------------------------------*/
247:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
248:lib/CMSIS/Core/CM3/system_stm32f10x.c **** GPIOD->CRL = 0x44BB44BB;
249:lib/CMSIS/Core/CM3/system_stm32f10x.c **** GPIOD->CRH = 0xBBBBBBBB;
250:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
251:lib/CMSIS/Core/CM3/system_stm32f10x.c **** GPIOE->CRL = 0xB44444BB;
252:lib/CMSIS/Core/CM3/system_stm32f10x.c **** GPIOE->CRH = 0xBBBBBBBB;
253:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
254:lib/CMSIS/Core/CM3/system_stm32f10x.c **** GPIOF->CRL = 0x44BBBBBB;
255:lib/CMSIS/Core/CM3/system_stm32f10x.c **** GPIOF->CRH = 0xBBBB4444;
256:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
257:lib/CMSIS/Core/CM3/system_stm32f10x.c **** GPIOG->CRL = 0x44BBBBBB;
258:lib/CMSIS/Core/CM3/system_stm32f10x.c **** GPIOG->CRH = 0x44444B44;
259:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
260:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*---------------- FSMC Configuration ---------------------------------------*/
261:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
262:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
263:lib/CMSIS/Core/CM3/system_stm32f10x.c **** FSMC_Bank1->BTCR[4] = 0x00001011;
264:lib/CMSIS/Core/CM3/system_stm32f10x.c **** FSMC_Bank1->BTCR[5] = 0x00000200;
265:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
266:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #endif /* DATA_IN_ExtSRAM */
267:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
268:lib/CMSIS/Core/CM3/system_stm32f10x.c **** #ifdef SYSCLK_FREQ_HSE
269:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /**
270:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @brief Selects HSE as System clock source and configure HCLK, PCLK2
271:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * and PCLK1 prescalers.
272:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @param None.
273:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @arg None.
274:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @note : This function should be used only after reset.
275:lib/CMSIS/Core/CM3/system_stm32f10x.c **** * @retval value: None.
276:lib/CMSIS/Core/CM3/system_stm32f10x.c **** */
277:lib/CMSIS/Core/CM3/system_stm32f10x.c **** static void SetSysClockToHSE(void)
278:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
279:lib/CMSIS/Core/CM3/system_stm32f10x.c **** __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
280:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
281:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
282:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Enable HSE */
283:lib/CMSIS/Core/CM3/system_stm32f10x.c **** RCC->CR |= ((uint32_t)RCC_CR_HSEON);
284:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
285:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Wait till HSE is ready and if Time out is reached exit */
286:lib/CMSIS/Core/CM3/system_stm32f10x.c **** do
287:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
288:lib/CMSIS/Core/CM3/system_stm32f10x.c **** HSEStatus = RCC->CR & RCC_CR_HSERDY;
289:lib/CMSIS/Core/CM3/system_stm32f10x.c **** StartUpCounter++;
290:lib/CMSIS/Core/CM3/system_stm32f10x.c **** } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
291:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
292:lib/CMSIS/Core/CM3/system_stm32f10x.c **** if ((RCC->CR & RCC_CR_HSERDY) != RESET)
293:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
294:lib/CMSIS/Core/CM3/system_stm32f10x.c **** HSEStatus = (uint32_t)0x01;
295:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
296:lib/CMSIS/Core/CM3/system_stm32f10x.c **** else
297:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
298:lib/CMSIS/Core/CM3/system_stm32f10x.c **** HSEStatus = (uint32_t)0x00;
299:lib/CMSIS/Core/CM3/system_stm32f10x.c **** }
300:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
301:lib/CMSIS/Core/CM3/system_stm32f10x.c **** if (HSEStatus == (uint32_t)0x01)
302:lib/CMSIS/Core/CM3/system_stm32f10x.c **** {
303:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Enable Prefetch Buffer */
304:lib/CMSIS/Core/CM3/system_stm32f10x.c **** FLASH->ACR |= FLASH_ACR_PRFTBE;
305:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
306:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< Flash 0 wait state */
307:lib/CMSIS/Core/CM3/system_stm32f10x.c **** FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
308:lib/CMSIS/Core/CM3/system_stm32f10x.c **** FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
309:lib/CMSIS/Core/CM3/system_stm32f10x.c ****
310:lib/CMSIS/Core/CM3/system_stm32f10x.c **** /*!< HCLK = SYSCLK */
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