core_cm3.lst

STM32 "kickstart" program with newlib/stdio like sprintf&printf

   1              		.syntax unified
   2              		.cpu cortex-m3
   3              		.fpu softvfp
   4              		.eabi_attribute 20, 1
   5              		.eabi_attribute 21, 1
   6              		.eabi_attribute 23, 3
   7              		.eabi_attribute 24, 1
   8              		.eabi_attribute 25, 1
   9              		.eabi_attribute 26, 1
  10              		.eabi_attribute 30, 4
  11              		.eabi_attribute 18, 4
  12              		.thumb
  13              		.file	"core_cm3.c"
  21              	.Ltext0:
  22              		.section	.text.__get_PSP,"ax",%progbits
  23              		.align	2
  24              		.global	__get_PSP
  25              		.thumb
  26              		.thumb_func
  28              	__get_PSP:
  29              	.LFB2:
  30              		.file 1 "lib/CMSIS/Core/CM3/core_cm3.c"
   1:lib/CMSIS/Core/CM3/core_cm3.c **** /******************************************************************************
   2:lib/CMSIS/Core/CM3/core_cm3.c ****  * @file:    core_cm3.c
   3:lib/CMSIS/Core/CM3/core_cm3.c ****  * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File
   4:lib/CMSIS/Core/CM3/core_cm3.c ****  * @version: V1.10
   5:lib/CMSIS/Core/CM3/core_cm3.c ****  * @date:    24. Feb. 2009
   6:lib/CMSIS/Core/CM3/core_cm3.c ****  *----------------------------------------------------------------------------
   7:lib/CMSIS/Core/CM3/core_cm3.c ****  *
   8:lib/CMSIS/Core/CM3/core_cm3.c ****  * Copyright (C) 2009 ARM Limited. All rights reserved.
   9:lib/CMSIS/Core/CM3/core_cm3.c ****  *
  10:lib/CMSIS/Core/CM3/core_cm3.c ****  * ARM Limited (ARM) is supplying this software for use with Cortex-Mx 
  11:lib/CMSIS/Core/CM3/core_cm3.c ****  * processor based microcontrollers.  This file can be freely distributed 
  12:lib/CMSIS/Core/CM3/core_cm3.c ****  * within development tools that are supporting such ARM based processors. 
  13:lib/CMSIS/Core/CM3/core_cm3.c ****  *
  14:lib/CMSIS/Core/CM3/core_cm3.c ****  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  15:lib/CMSIS/Core/CM3/core_cm3.c ****  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  16:lib/CMSIS/Core/CM3/core_cm3.c ****  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  17:lib/CMSIS/Core/CM3/core_cm3.c ****  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  18:lib/CMSIS/Core/CM3/core_cm3.c ****  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  19:lib/CMSIS/Core/CM3/core_cm3.c ****  *
  20:lib/CMSIS/Core/CM3/core_cm3.c ****  ******************************************************************************/
  21:lib/CMSIS/Core/CM3/core_cm3.c **** 
  22:lib/CMSIS/Core/CM3/core_cm3.c **** 
  23:lib/CMSIS/Core/CM3/core_cm3.c **** 
  24:lib/CMSIS/Core/CM3/core_cm3.c **** #include <stdint.h>
  25:lib/CMSIS/Core/CM3/core_cm3.c **** 
  26:lib/CMSIS/Core/CM3/core_cm3.c **** 
  27:lib/CMSIS/Core/CM3/core_cm3.c **** /* define compiler specific symbols */
  28:lib/CMSIS/Core/CM3/core_cm3.c **** #if defined   ( __CC_ARM   )
  29:lib/CMSIS/Core/CM3/core_cm3.c ****   #define __ASM            __asm           /*!< asm keyword for armcc          */
  30:lib/CMSIS/Core/CM3/core_cm3.c ****   #define __INLINE         __inline        /*!< inline keyword for armcc        */
  31:lib/CMSIS/Core/CM3/core_cm3.c **** 
  32:lib/CMSIS/Core/CM3/core_cm3.c **** #elif defined ( __ICCARM__ )
  33:lib/CMSIS/Core/CM3/core_cm3.c ****   #define __ASM           __asm            /*!< asm keyword for iarcc           */
  34:lib/CMSIS/Core/CM3/core_cm3.c ****   #define __INLINE        inline           /*!< inline keyword for iarcc. Only avaiable in High opt
  35:lib/CMSIS/Core/CM3/core_cm3.c ****   #define __nop           __no_operation   /*!< no operation intrinsic in iarcc */
  36:lib/CMSIS/Core/CM3/core_cm3.c **** 
  37:lib/CMSIS/Core/CM3/core_cm3.c **** #elif defined (  __GNUC__  )
  38:lib/CMSIS/Core/CM3/core_cm3.c ****   #define __ASM             asm            /*!< asm keyword for gcc            */
  39:lib/CMSIS/Core/CM3/core_cm3.c ****   #define __INLINE          inline         /*!< inline keyword for gcc         */
  40:lib/CMSIS/Core/CM3/core_cm3.c **** #endif
  41:lib/CMSIS/Core/CM3/core_cm3.c **** 
  42:lib/CMSIS/Core/CM3/core_cm3.c **** 
  43:lib/CMSIS/Core/CM3/core_cm3.c **** 
  44:lib/CMSIS/Core/CM3/core_cm3.c **** #if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
  45:lib/CMSIS/Core/CM3/core_cm3.c **** 
  46:lib/CMSIS/Core/CM3/core_cm3.c **** /**
  47:lib/CMSIS/Core/CM3/core_cm3.c ****  * @brief  Return the Process Stack Pointer
  48:lib/CMSIS/Core/CM3/core_cm3.c ****  *
  49:lib/CMSIS/Core/CM3/core_cm3.c ****  * @param  none
  50:lib/CMSIS/Core/CM3/core_cm3.c ****  * @return uint32_t ProcessStackPointer
  51:lib/CMSIS/Core/CM3/core_cm3.c ****  *
  52:lib/CMSIS/Core/CM3/core_cm3.c ****  * Return the actual process stack pointer
  53:lib/CMSIS/Core/CM3/core_cm3.c ****  */
  54:lib/CMSIS/Core/CM3/core_cm3.c **** __ASM uint32_t __get_PSP(void)
  55:lib/CMSIS/Core/CM3/core_cm3.c **** {
  56:lib/CMSIS/Core/CM3/core_cm3.c ****   mrs r0, psp
  57:lib/CMSIS/Core/CM3/core_cm3.c ****   bx lr
  58:lib/CMSIS/Core/CM3/core_cm3.c **** }
  59:lib/CMSIS/Core/CM3/core_cm3.c **** 
  60:lib/CMSIS/Core/CM3/core_cm3.c **** /**
  61:lib/CMSIS/Core/CM3/core_cm3.c ****  * @brief  Set the Process Stack Pointer
  62:lib/CMSIS/Core/CM3/core_cm3.c ****  *
  63:lib/CMSIS/Core/CM3/core_cm3.c ****  * @param  uint32_t Process Stack Pointer
  64:lib/CMSIS/Core/CM3/core_cm3.c ****  * @return none
  65:lib/CMSIS/Core/CM3/core_cm3.c ****  *
  66:lib/CMSIS/Core/CM3/core_cm3.c ****  * Assign the value ProcessStackPointer to the MSP 
  67:lib/CMSIS/Core/CM3/core_cm3.c ****  * (process stack pointer) Cortex processor register
  68:lib/CMSIS/Core/CM3/core_cm3.c ****  */
  69:lib/CMSIS/Core/CM3/core_cm3.c **** __ASM void __set_PSP(uint32_t topOfProcStack)
  70:lib/CMSIS/Core/CM3/core_cm3.c **** {
  71:lib/CMSIS/Core/CM3/core_cm3.c ****   msr psp, r0
  72:lib/CMSIS/Core/CM3/core_cm3.c ****   bx lr
  73:lib/CMSIS/Core/CM3/core_cm3.c **** }
  74:lib/CMSIS/Core/CM3/core_cm3.c **** 
  75:lib/CMSIS/Core/CM3/core_cm3.c **** /**
  76:lib/CMSIS/Core/CM3/core_cm3.c ****  * @brief  Return the Main Stack Pointer
  77:lib/CMSIS/Core/CM3/core_cm3.c ****  *
  78:lib/CMSIS/Core/CM3/core_cm3.c ****  * @param  none
  79:lib/CMSIS/Core/CM3/core_cm3.c ****  * @return uint32_t Main Stack Pointer
  80:lib/CMSIS/Core/CM3/core_cm3.c ****  *
  81:lib/CMSIS/Core/CM3/core_cm3.c ****  * Return the current value of the MSP (main stack pointer)
  82:lib/CMSIS/Core/CM3/core_cm3.c ****  * Cortex processor register
  83:lib/CMSIS/Core/CM3/core_cm3.c ****  */
  84:lib/CMSIS/Core/CM3/core_cm3.c **** __ASM uint32_t __get_MSP(void)
  85:lib/CMSIS/Core/CM3/core_cm3.c **** {
  86:lib/CMSIS/Core/CM3/core_cm3.c ****   mrs r0, msp
  87:lib/CMSIS/Core/CM3/core_cm3.c ****   bx lr
  88:lib/CMSIS/Core/CM3/core_cm3.c **** }
  89:lib/CMSIS/Core/CM3/core_cm3.c **** 
  90:lib/CMSIS/Core/CM3/core_cm3.c **** /**
  91:lib/CMSIS/Core/CM3/core_cm3.c ****  * @brief  Set the Main Stack Pointer
  92:lib/CMSIS/Core/CM3/core_cm3.c ****  *
  93:lib/CMSIS/Core/CM3/core_cm3.c ****  * @param  uint32_t Main Stack Pointer
  94:lib/CMSIS/Core/CM3/core_cm3.c ****  * @return none
  95:lib/CMSIS/Core/CM3/core_cm3.c ****  *
  96:lib/CMSIS/Core/CM3/core_cm3.c ****  * Assign the value mainStackPointer to the MSP 
  97:lib/CMSIS/Core/CM3/core_cm3.c ****  * (main stack pointer) Cortex processor register
  98:lib/CMSIS/Core/CM3/core_cm3.c ****  */
  99:lib/CMSIS/Core/CM3/core_cm3.c **** __ASM void __set_MSP(uint32_t mainStackPointer)
 100:lib/CMSIS/Core/CM3/core_cm3.c **** {
 101:lib/CMSIS/Core/CM3/core_cm3.c ****   msr msp, r0
 102:lib/CMSIS/Core/CM3/core_cm3.c ****   bx lr
 103:lib/CMSIS/Core/CM3/core_cm3.c **** }
 104:lib/CMSIS/Core/CM3/core_cm3.c **** 
 105:lib/CMSIS/Core/CM3/core_cm3.c **** /**
 106:lib/CMSIS/Core/CM3/core_cm3.c ****  * @brief  Reverse byte order in unsigned short value
 107:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 108:lib/CMSIS/Core/CM3/core_cm3.c ****  * @param  uint16_t value to reverse
 109:lib/CMSIS/Core/CM3/core_cm3.c ****  * @return uint32_t reversed value
 110:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 111:lib/CMSIS/Core/CM3/core_cm3.c ****  * Reverse byte order in unsigned short value
 112:lib/CMSIS/Core/CM3/core_cm3.c ****  */
 113:lib/CMSIS/Core/CM3/core_cm3.c **** __ASM uint32_t __REV16(uint16_t value)
 114:lib/CMSIS/Core/CM3/core_cm3.c **** {
 115:lib/CMSIS/Core/CM3/core_cm3.c ****   rev16 r0, r0
 116:lib/CMSIS/Core/CM3/core_cm3.c ****   bx lr
 117:lib/CMSIS/Core/CM3/core_cm3.c **** }
 118:lib/CMSIS/Core/CM3/core_cm3.c **** 
 119:lib/CMSIS/Core/CM3/core_cm3.c **** /**
 120:lib/CMSIS/Core/CM3/core_cm3.c ****  * @brief  Reverse byte order in signed short value with sign extension to integer
 121:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 122:lib/CMSIS/Core/CM3/core_cm3.c ****  * @param  int16_t value to reverse
 123:lib/CMSIS/Core/CM3/core_cm3.c ****  * @return int32_t reversed value
 124:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 125:lib/CMSIS/Core/CM3/core_cm3.c ****  * Reverse byte order in signed short value with sign extension to integer
 126:lib/CMSIS/Core/CM3/core_cm3.c ****  */
 127:lib/CMSIS/Core/CM3/core_cm3.c **** __ASM int32_t __REVSH(int16_t value)
 128:lib/CMSIS/Core/CM3/core_cm3.c **** {
 129:lib/CMSIS/Core/CM3/core_cm3.c ****   revsh r0, r0
 130:lib/CMSIS/Core/CM3/core_cm3.c ****   bx lr
 131:lib/CMSIS/Core/CM3/core_cm3.c **** }
 132:lib/CMSIS/Core/CM3/core_cm3.c **** 
 133:lib/CMSIS/Core/CM3/core_cm3.c **** 
 134:lib/CMSIS/Core/CM3/core_cm3.c **** #if (__ARMCC_VERSION < 400000)
 135:lib/CMSIS/Core/CM3/core_cm3.c **** 
 136:lib/CMSIS/Core/CM3/core_cm3.c **** /**
 137:lib/CMSIS/Core/CM3/core_cm3.c ****  * @brief  Remove the exclusive lock created by ldrex
 138:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 139:lib/CMSIS/Core/CM3/core_cm3.c ****  * @param  none
 140:lib/CMSIS/Core/CM3/core_cm3.c ****  * @return none
 141:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 142:lib/CMSIS/Core/CM3/core_cm3.c ****  * Removes the exclusive lock which is created by ldrex.
 143:lib/CMSIS/Core/CM3/core_cm3.c ****  */
 144:lib/CMSIS/Core/CM3/core_cm3.c **** __ASM void __CLREX(void)
 145:lib/CMSIS/Core/CM3/core_cm3.c **** {
 146:lib/CMSIS/Core/CM3/core_cm3.c ****   clrex
 147:lib/CMSIS/Core/CM3/core_cm3.c **** }
 148:lib/CMSIS/Core/CM3/core_cm3.c **** 
 149:lib/CMSIS/Core/CM3/core_cm3.c **** /**
 150:lib/CMSIS/Core/CM3/core_cm3.c ****  * @brief  Return the Base Priority value
 151:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 152:lib/CMSIS/Core/CM3/core_cm3.c ****  * @param  none
 153:lib/CMSIS/Core/CM3/core_cm3.c ****  * @return uint32_t BasePriority
 154:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 155:lib/CMSIS/Core/CM3/core_cm3.c ****  * Return the content of the base priority register
 156:lib/CMSIS/Core/CM3/core_cm3.c ****  */
 157:lib/CMSIS/Core/CM3/core_cm3.c **** __ASM uint32_t  __get_BASEPRI(void)
 158:lib/CMSIS/Core/CM3/core_cm3.c **** {
 159:lib/CMSIS/Core/CM3/core_cm3.c ****   mrs r0, basepri
 160:lib/CMSIS/Core/CM3/core_cm3.c ****   bx lr
 161:lib/CMSIS/Core/CM3/core_cm3.c **** }
 162:lib/CMSIS/Core/CM3/core_cm3.c **** 
 163:lib/CMSIS/Core/CM3/core_cm3.c **** /**
 164:lib/CMSIS/Core/CM3/core_cm3.c ****  * @brief  Set the Base Priority value
 165:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 166:lib/CMSIS/Core/CM3/core_cm3.c ****  * @param  uint32_t BasePriority
 167:lib/CMSIS/Core/CM3/core_cm3.c ****  * @return none
 168:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 169:lib/CMSIS/Core/CM3/core_cm3.c ****  * Set the base priority register
 170:lib/CMSIS/Core/CM3/core_cm3.c ****  */
 171:lib/CMSIS/Core/CM3/core_cm3.c **** __ASM void __set_BASEPRI(uint32_t basePri)
 172:lib/CMSIS/Core/CM3/core_cm3.c **** {
 173:lib/CMSIS/Core/CM3/core_cm3.c ****   msr basepri, r0
 174:lib/CMSIS/Core/CM3/core_cm3.c ****   bx lr
 175:lib/CMSIS/Core/CM3/core_cm3.c **** }
 176:lib/CMSIS/Core/CM3/core_cm3.c **** 
 177:lib/CMSIS/Core/CM3/core_cm3.c **** /**
 178:lib/CMSIS/Core/CM3/core_cm3.c ****  * @brief  Return the Priority Mask value
 179:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 180:lib/CMSIS/Core/CM3/core_cm3.c ****  * @param  none
 181:lib/CMSIS/Core/CM3/core_cm3.c ****  * @return uint32_t PriMask
 182:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 183:lib/CMSIS/Core/CM3/core_cm3.c ****  * Return the state of the priority mask bit from the priority mask
 184:lib/CMSIS/Core/CM3/core_cm3.c ****  * register
 185:lib/CMSIS/Core/CM3/core_cm3.c ****  */
 186:lib/CMSIS/Core/CM3/core_cm3.c **** __ASM uint32_t __get_PRIMASK(void)
 187:lib/CMSIS/Core/CM3/core_cm3.c **** {
 188:lib/CMSIS/Core/CM3/core_cm3.c ****   mrs r0, primask
 189:lib/CMSIS/Core/CM3/core_cm3.c ****   bx lr
 190:lib/CMSIS/Core/CM3/core_cm3.c **** }
 191:lib/CMSIS/Core/CM3/core_cm3.c **** 
 192:lib/CMSIS/Core/CM3/core_cm3.c **** /**
 193:lib/CMSIS/Core/CM3/core_cm3.c ****  * @brief  Set the Priority Mask value
 194:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 195:lib/CMSIS/Core/CM3/core_cm3.c ****  * @param  uint32_t PriMask
 196:lib/CMSIS/Core/CM3/core_cm3.c ****  * @return none
 197:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 198:lib/CMSIS/Core/CM3/core_cm3.c ****  * Set the priority mask bit in the priority mask register
 199:lib/CMSIS/Core/CM3/core_cm3.c ****  */
 200:lib/CMSIS/Core/CM3/core_cm3.c **** __ASM void __set_PRIMASK(uint32_t priMask)
 201:lib/CMSIS/Core/CM3/core_cm3.c **** {
 202:lib/CMSIS/Core/CM3/core_cm3.c ****   msr primask, r0
 203:lib/CMSIS/Core/CM3/core_cm3.c ****   bx lr
 204:lib/CMSIS/Core/CM3/core_cm3.c **** }
 205:lib/CMSIS/Core/CM3/core_cm3.c **** 
 206:lib/CMSIS/Core/CM3/core_cm3.c **** /**
 207:lib/CMSIS/Core/CM3/core_cm3.c ****  * @brief  Return the Fault Mask value
 208:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 209:lib/CMSIS/Core/CM3/core_cm3.c ****  * @param  none
 210:lib/CMSIS/Core/CM3/core_cm3.c ****  * @return uint32_t FaultMask
 211:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 212:lib/CMSIS/Core/CM3/core_cm3.c ****  * Return the content of the fault mask register
 213:lib/CMSIS/Core/CM3/core_cm3.c ****  */
 214:lib/CMSIS/Core/CM3/core_cm3.c **** __ASM uint32_t  __get_FAULTMASK(void)
 215:lib/CMSIS/Core/CM3/core_cm3.c **** {
 216:lib/CMSIS/Core/CM3/core_cm3.c ****   mrs r0, faultmask
 217:lib/CMSIS/Core/CM3/core_cm3.c ****   bx lr
 218:lib/CMSIS/Core/CM3/core_cm3.c **** }
 219:lib/CMSIS/Core/CM3/core_cm3.c **** 
 220:lib/CMSIS/Core/CM3/core_cm3.c **** /**
 221:lib/CMSIS/Core/CM3/core_cm3.c ****  * @brief  Set the Fault Mask value
 222:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 223:lib/CMSIS/Core/CM3/core_cm3.c ****  * @param  uint32_t faultMask value
 224:lib/CMSIS/Core/CM3/core_cm3.c ****  * @return none
 225:lib/CMSIS/Core/CM3/core_cm3.c ****  *
 226:lib/CMSIS/Core/CM3/core_cm3.c ****  * Set the fault mask register
 227:lib/CMSIS/Core/CM3/core_cm3.c ****  */
 228:lib/CMSIS/Core/CM3/core_cm3.c **** __ASM void __set_FAULTMASK(uint32_t faultMask)
 229:lib/CMSIS/Core/CM3/core_cm3.c **** {
 230:lib/CMSIS/Core/CM3/core_cm3.c ****   msr faultmask, r0