📄 stm32f10x_pwr.lst
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155:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t SCR; /*!< System Control Register
156:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t CCR; /*!< Configuration Control Register
157:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 1
158:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t SHCSR; /*!< System Handler Control and State Register
159:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t CFSR; /*!< Configurable Fault Status Register
160:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t HFSR; /*!< Hard Fault Status Register
161:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t DFSR; /*!< Debug Fault Status Register
162:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t MMFAR; /*!< Mem Manage Address Register
163:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t BFAR; /*!< Bus Fault Address Register
164:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register
165:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t PFR[2]; /*!< Processor Feature Register
166:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t DFR; /*!< Debug Feature Register
167:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t ADR; /*!< Auxiliary Feature Register
168:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t MMFR[4]; /*!< Memory Model Feature Register
169:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t ISAR[5]; /*!< ISA Feature Register
170:./lib/CMSIS/Core/CM3/core_cm3.h **** } SCB_Type;
171:./lib/CMSIS/Core/CM3/core_cm3.h ****
172:./lib/CMSIS/Core/CM3/core_cm3.h ****
173:./lib/CMSIS/Core/CM3/core_cm3.h **** /* memory mapping struct for SysTick */
174:./lib/CMSIS/Core/CM3/core_cm3.h **** typedef struct
175:./lib/CMSIS/Core/CM3/core_cm3.h **** {
176:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t CTRL; /*!< SysTick Control and Status Register */
177:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t LOAD; /*!< SysTick Reload Value Register */
178:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t VAL; /*!< SysTick Current Value Register */
179:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t CALIB; /*!< SysTick Calibration Register */
180:./lib/CMSIS/Core/CM3/core_cm3.h **** } SysTick_Type;
181:./lib/CMSIS/Core/CM3/core_cm3.h ****
182:./lib/CMSIS/Core/CM3/core_cm3.h ****
183:./lib/CMSIS/Core/CM3/core_cm3.h **** /* memory mapping structur for ITM */
184:./lib/CMSIS/Core/CM3/core_cm3.h **** typedef struct
185:./lib/CMSIS/Core/CM3/core_cm3.h **** {
186:./lib/CMSIS/Core/CM3/core_cm3.h **** __O union
187:./lib/CMSIS/Core/CM3/core_cm3.h **** {
188:./lib/CMSIS/Core/CM3/core_cm3.h **** __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */
189:./lib/CMSIS/Core/CM3/core_cm3.h **** __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */
190:./lib/CMSIS/Core/CM3/core_cm3.h **** __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */
191:./lib/CMSIS/Core/CM3/core_cm3.h **** } PORT [32]; /*!< ITM Stimulus Port Registers */
192:./lib/CMSIS/Core/CM3/core_cm3.h **** uint32_t RESERVED0[864];
193:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t TER; /*!< ITM Trace Enable Register */
194:./lib/CMSIS/Core/CM3/core_cm3.h **** uint32_t RESERVED1[15];
195:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t TPR; /*!< ITM Trace Privilege Register */
196:./lib/CMSIS/Core/CM3/core_cm3.h **** uint32_t RESERVED2[15];
197:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t TCR; /*!< ITM Trace Control Register */
198:./lib/CMSIS/Core/CM3/core_cm3.h **** uint32_t RESERVED3[29];
199:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t IWR; /*!< ITM Integration Write Register */
200:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t IRR; /*!< ITM Integration Read Register */
201:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */
202:./lib/CMSIS/Core/CM3/core_cm3.h **** uint32_t RESERVED4[43];
203:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t LAR; /*!< ITM Lock Access Register */
204:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t LSR; /*!< ITM Lock Status Register */
205:./lib/CMSIS/Core/CM3/core_cm3.h **** uint32_t RESERVED5[6];
206:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t PID4; /*!< ITM Product ID Registers */
207:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t PID5;
208:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t PID6;
209:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t PID7;
210:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t PID0;
211:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t PID1;
212:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t PID2;
213:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t PID3;
214:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t CID0;
215:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t CID1;
216:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t CID2;
217:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t CID3;
218:./lib/CMSIS/Core/CM3/core_cm3.h **** } ITM_Type;
219:./lib/CMSIS/Core/CM3/core_cm3.h ****
220:./lib/CMSIS/Core/CM3/core_cm3.h ****
221:./lib/CMSIS/Core/CM3/core_cm3.h **** /* memory mapped struct for Interrupt Type */
222:./lib/CMSIS/Core/CM3/core_cm3.h **** typedef struct
223:./lib/CMSIS/Core/CM3/core_cm3.h **** {
224:./lib/CMSIS/Core/CM3/core_cm3.h **** uint32_t RESERVED0;
225:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t ICTR; /*!< Interrupt Control Type Register */
226:./lib/CMSIS/Core/CM3/core_cm3.h **** #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
227:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t ACTLR; /*!< Auxiliary Control Register */
228:./lib/CMSIS/Core/CM3/core_cm3.h **** #else
229:./lib/CMSIS/Core/CM3/core_cm3.h **** uint32_t RESERVED1;
230:./lib/CMSIS/Core/CM3/core_cm3.h **** #endif
231:./lib/CMSIS/Core/CM3/core_cm3.h **** } InterruptType_Type;
232:./lib/CMSIS/Core/CM3/core_cm3.h ****
233:./lib/CMSIS/Core/CM3/core_cm3.h ****
234:./lib/CMSIS/Core/CM3/core_cm3.h **** /* Memory Protection Unit */
235:./lib/CMSIS/Core/CM3/core_cm3.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
236:./lib/CMSIS/Core/CM3/core_cm3.h **** typedef struct
237:./lib/CMSIS/Core/CM3/core_cm3.h **** {
238:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t TYPE; /*!< MPU Type Register
239:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t CTRL; /*!< MPU Control Register
240:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t RNR; /*!< MPU Region RNRber Register
241:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t RBAR; /*!< MPU Region Base Address Register
242:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register
243:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register
244:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register
245:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register
246:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register
247:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register
248:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register
249:./lib/CMSIS/Core/CM3/core_cm3.h **** } MPU_Type;
250:./lib/CMSIS/Core/CM3/core_cm3.h **** #endif
251:./lib/CMSIS/Core/CM3/core_cm3.h ****
252:./lib/CMSIS/Core/CM3/core_cm3.h ****
253:./lib/CMSIS/Core/CM3/core_cm3.h **** /* Core Debug Register */
254:./lib/CMSIS/Core/CM3/core_cm3.h **** typedef struct
255:./lib/CMSIS/Core/CM3/core_cm3.h **** {
256:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register
257:./lib/CMSIS/Core/CM3/core_cm3.h **** __O uint32_t DCRSR; /*!< Debug Core Register Selector Register
258:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t DCRDR; /*!< Debug Core Register Data Register
259:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register
260:./lib/CMSIS/Core/CM3/core_cm3.h **** } CoreDebug_Type;
261:./lib/CMSIS/Core/CM3/core_cm3.h ****
262:./lib/CMSIS/Core/CM3/core_cm3.h ****
263:./lib/CMSIS/Core/CM3/core_cm3.h **** /* Memory mapping of Cortex-M3 Hardware */
264:./lib/CMSIS/Core/CM3/core_cm3.h **** #define SCS_BASE (0xE000E000) /*!< System Control Space Bas
265:./lib/CMSIS/Core/CM3/core_cm3.h **** #define ITM_BASE (0xE0000000) /*!< ITM Base Address
266:./lib/CMSIS/Core/CM3/core_cm3.h **** #define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address
267:./lib/CMSIS/Core/CM3/core_cm3.h **** #define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address
268:./lib/CMSIS/Core/CM3/core_cm3.h **** #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address
269:./lib/CMSIS/Core/CM3/core_cm3.h **** #define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Bas
270:./lib/CMSIS/Core/CM3/core_cm3.h ****
271:./lib/CMSIS/Core/CM3/core_cm3.h **** #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register
272:./lib/CMSIS/Core/CM3/core_cm3.h **** #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct
273:./lib/CMSIS/Core/CM3/core_cm3.h **** #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration st
274:./lib/CMSIS/Core/CM3/core_cm3.h **** #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struc
275:./lib/CMSIS/Core/CM3/core_cm3.h **** #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct
276:./lib/CMSIS/Core/CM3/core_cm3.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration
277:./lib/CMSIS/Core/CM3/core_cm3.h ****
278:./lib/CMSIS/Core/CM3/core_cm3.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
279:./lib/CMSIS/Core/CM3/core_cm3.h **** #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit
280:./lib/CMSIS/Core/CM3/core_cm3.h **** #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit
281:./lib/CMSIS/Core/CM3/core_cm3.h **** #endif
282:./lib/CMSIS/Core/CM3/core_cm3.h ****
283:./lib/CMSIS/Core/CM3/core_cm3.h ****
284:./lib/CMSIS/Core/CM3/core_cm3.h ****
285:./lib/CMSIS/Core/CM3/core_cm3.h **** /*******************************************************************************
286:./lib/CMSIS/Core/CM3/core_cm3.h **** * Hardware Abstraction Layer
287:./lib/CMSIS/Core/CM3/core_cm3.h **** ******************************************************************************/
288:./lib/CMSIS/Core/CM3/core_cm3.h ****
289:./lib/CMSIS/Core/CM3/core_cm3.h ****
290:./lib/CMSIS/Core/CM3/core_cm3.h **** #if defined ( __CC_ARM )
291:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __ASM __asm /*!< asm keyword for ARM Comp
292:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __INLINE __inline /*!< inline keyword for ARM C
293:./lib/CMSIS/Core/CM3/core_cm3.h ****
294:./lib/CMSIS/Core/CM3/core_cm3.h **** #elif defined ( __ICCARM__ )
295:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __ASM __asm /*!< asm keyword for IAR Comp
296:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __INLINE inline /*!< inline keyword for IAR C
297:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __NOP __no_operation /*!< no operation intrinsic i
298:./lib/CMSIS/Core/CM3/core_cm3.h ****
299:./lib/CMSIS/Core/CM3/core_cm3.h **** #elif defined ( __GNUC__ )
300:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __ASM asm /*!< asm keyword for GNU Comp
301:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __INLINE inline /*!< inline keyword for GNU C
302:./lib/CMSIS/Core/CM3/core_cm3.h ****
303:./lib/CMSIS/Core/CM3/core_cm3.h **** #endif
304:./lib/CMSIS/Core/CM3/core_cm3.h ****
305:./lib/CMSIS/Core/CM3/core_cm3.h ****
306:./lib/CMSIS/Core/CM3/core_cm3.h **** /* ################### Compiler specific Intrinsics ########################### */
307:./lib/CMSIS/Core/CM3/core_cm3.h ****
308:./lib/CMSIS/Core/CM3/core_cm3.h **** #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
309:./lib/CMSIS/Core/CM3/core_cm3.h **** /* ARM armcc specific functions */
310:./lib/CMSIS/Core/CM3/core_cm3.h ****
311:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __enable_fault_irq __enable_fiq
312:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __disable_fault_irq __disable_fiq
313:./lib/CMSIS/Core/CM3/core_cm3.h ****
314:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __NOP __nop
315:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __WFI __wfi
316:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __WFE __wfe
317:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __SEV __sev
318:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __ISB() __isb(0)
319:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __DSB() __dsb(0)
320:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __DMB() __dmb(0)
321:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __REV __rev
322:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __RBIT __rbit
323:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
324:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
325:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
326:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __STREXB(value, ptr) __strex(value, ptr)
327:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __STREXH(value, ptr) __strex(value, ptr)
328:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __STREXW(value, ptr) __strex(value, ptr)
329:./lib/CMSIS/Core/CM3/core_cm3.h ****
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