📄 stm32f10x_pwr.lst
字号:
1 .syntax unified
2 .cpu cortex-m3
3 .fpu softvfp
4 .eabi_attribute 20, 1
5 .eabi_attribute 21, 1
6 .eabi_attribute 23, 3
7 .eabi_attribute 24, 1
8 .eabi_attribute 25, 1
9 .eabi_attribute 26, 1
10 .eabi_attribute 30, 4
11 .eabi_attribute 18, 4
12 .thumb
13 .file "stm32f10x_pwr.c"
21 .Ltext0:
22 .section .text.__WFI,"ax",%progbits
23 .align 2
24 .thumb
25 .thumb_func
27 __WFI:
28 .LFB7:
29 .file 1 "./lib/CMSIS/Core/CM3/core_cm3.h"
1:./lib/CMSIS/Core/CM3/core_cm3.h **** /******************************************************************************
2:./lib/CMSIS/Core/CM3/core_cm3.h **** * @file: core_cm3.h
3:./lib/CMSIS/Core/CM3/core_cm3.h **** * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
4:./lib/CMSIS/Core/CM3/core_cm3.h **** * @version: V1.10
5:./lib/CMSIS/Core/CM3/core_cm3.h **** * @date: 24. Feb. 2009
6:./lib/CMSIS/Core/CM3/core_cm3.h **** *----------------------------------------------------------------------------
7:./lib/CMSIS/Core/CM3/core_cm3.h **** *
8:./lib/CMSIS/Core/CM3/core_cm3.h **** * Copyright (C) 2009 ARM Limited. All rights reserved.
9:./lib/CMSIS/Core/CM3/core_cm3.h **** *
10:./lib/CMSIS/Core/CM3/core_cm3.h **** * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
11:./lib/CMSIS/Core/CM3/core_cm3.h **** * processor based microcontrollers. This file can be freely distributed
12:./lib/CMSIS/Core/CM3/core_cm3.h **** * within development tools that are supporting such ARM based processors.
13:./lib/CMSIS/Core/CM3/core_cm3.h **** *
14:./lib/CMSIS/Core/CM3/core_cm3.h **** * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
15:./lib/CMSIS/Core/CM3/core_cm3.h **** * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
16:./lib/CMSIS/Core/CM3/core_cm3.h **** * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
17:./lib/CMSIS/Core/CM3/core_cm3.h **** * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
18:./lib/CMSIS/Core/CM3/core_cm3.h **** * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
19:./lib/CMSIS/Core/CM3/core_cm3.h **** *
20:./lib/CMSIS/Core/CM3/core_cm3.h **** ******************************************************************************/
21:./lib/CMSIS/Core/CM3/core_cm3.h ****
22:./lib/CMSIS/Core/CM3/core_cm3.h ****
23:./lib/CMSIS/Core/CM3/core_cm3.h ****
24:./lib/CMSIS/Core/CM3/core_cm3.h ****
25:./lib/CMSIS/Core/CM3/core_cm3.h **** #ifndef __CM3_CORE_H__
26:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __CM3_CORE_H__
27:./lib/CMSIS/Core/CM3/core_cm3.h ****
28:./lib/CMSIS/Core/CM3/core_cm3.h ****
29:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!<
30:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __CM3_CMSIS_VERSION_SUB (0x10) /*!<
31:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!<
32:./lib/CMSIS/Core/CM3/core_cm3.h ****
33:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __CORTEX_M (0x03) /*!<
34:./lib/CMSIS/Core/CM3/core_cm3.h ****
35:./lib/CMSIS/Core/CM3/core_cm3.h **** /**
36:./lib/CMSIS/Core/CM3/core_cm3.h **** * Lint configuration \n
37:./lib/CMSIS/Core/CM3/core_cm3.h **** * ----------------------- \n
38:./lib/CMSIS/Core/CM3/core_cm3.h **** *
39:./lib/CMSIS/Core/CM3/core_cm3.h **** * The following Lint messages will be suppressed and not shown: \n
40:./lib/CMSIS/Core/CM3/core_cm3.h **** * \n
41:./lib/CMSIS/Core/CM3/core_cm3.h **** * --- Error 10: --- \n
42:./lib/CMSIS/Core/CM3/core_cm3.h **** * register uint32_t __regBasePri __asm("basepri"); \n
43:./lib/CMSIS/Core/CM3/core_cm3.h **** * Error 10: Expecting ';' \n
44:./lib/CMSIS/Core/CM3/core_cm3.h **** * \n
45:./lib/CMSIS/Core/CM3/core_cm3.h **** * --- Error 530: --- \n
46:./lib/CMSIS/Core/CM3/core_cm3.h **** * return(__regBasePri); \n
47:./lib/CMSIS/Core/CM3/core_cm3.h **** * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
48:./lib/CMSIS/Core/CM3/core_cm3.h **** * \n
49:./lib/CMSIS/Core/CM3/core_cm3.h **** * --- Error 550: --- \n
50:./lib/CMSIS/Core/CM3/core_cm3.h **** * __regBasePri = (basePri & 0x1ff); \n
51:./lib/CMSIS/Core/CM3/core_cm3.h **** * } \n
52:./lib/CMSIS/Core/CM3/core_cm3.h **** * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
53:./lib/CMSIS/Core/CM3/core_cm3.h **** * \n
54:./lib/CMSIS/Core/CM3/core_cm3.h **** * --- Error 754: --- \n
55:./lib/CMSIS/Core/CM3/core_cm3.h **** * uint32_t RESERVED0[24]; \n
56:./lib/CMSIS/Core/CM3/core_cm3.h **** * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h)
57:./lib/CMSIS/Core/CM3/core_cm3.h **** * \n
58:./lib/CMSIS/Core/CM3/core_cm3.h **** * --- Error 750: --- \n
59:./lib/CMSIS/Core/CM3/core_cm3.h **** * #define __CM3_CORE_H__ \n
60:./lib/CMSIS/Core/CM3/core_cm3.h **** * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
61:./lib/CMSIS/Core/CM3/core_cm3.h **** * \n
62:./lib/CMSIS/Core/CM3/core_cm3.h **** * --- Error 528: --- \n
63:./lib/CMSIS/Core/CM3/core_cm3.h **** * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
64:./lib/CMSIS/Core/CM3/core_cm3.h **** * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referen
65:./lib/CMSIS/Core/CM3/core_cm3.h **** * \n
66:./lib/CMSIS/Core/CM3/core_cm3.h **** * --- Error 751: --- \n
67:./lib/CMSIS/Core/CM3/core_cm3.h **** * } InterruptType_Type; \n
68:./lib/CMSIS/Core/CM3/core_cm3.h **** * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
69:./lib/CMSIS/Core/CM3/core_cm3.h **** * \n
70:./lib/CMSIS/Core/CM3/core_cm3.h **** * \n
71:./lib/CMSIS/Core/CM3/core_cm3.h **** * Note: To re-enable a Message, insert a space before 'lint' * \n
72:./lib/CMSIS/Core/CM3/core_cm3.h **** *
73:./lib/CMSIS/Core/CM3/core_cm3.h **** */
74:./lib/CMSIS/Core/CM3/core_cm3.h ****
75:./lib/CMSIS/Core/CM3/core_cm3.h **** /*lint -save */
76:./lib/CMSIS/Core/CM3/core_cm3.h **** /*lint -e10 */
77:./lib/CMSIS/Core/CM3/core_cm3.h **** /*lint -e530 */
78:./lib/CMSIS/Core/CM3/core_cm3.h **** /*lint -e550 */
79:./lib/CMSIS/Core/CM3/core_cm3.h **** /*lint -e754 */
80:./lib/CMSIS/Core/CM3/core_cm3.h **** /*lint -e750 */
81:./lib/CMSIS/Core/CM3/core_cm3.h **** /*lint -e528 */
82:./lib/CMSIS/Core/CM3/core_cm3.h **** /*lint -e751 */
83:./lib/CMSIS/Core/CM3/core_cm3.h ****
84:./lib/CMSIS/Core/CM3/core_cm3.h ****
85:./lib/CMSIS/Core/CM3/core_cm3.h **** #include <stdint.h> /* Include standard types */
86:./lib/CMSIS/Core/CM3/core_cm3.h ****
87:./lib/CMSIS/Core/CM3/core_cm3.h **** #if defined (__ICCARM__)
88:./lib/CMSIS/Core/CM3/core_cm3.h **** #include <intrinsics.h> /* IAR Intrinsics */
89:./lib/CMSIS/Core/CM3/core_cm3.h **** #endif
90:./lib/CMSIS/Core/CM3/core_cm3.h ****
91:./lib/CMSIS/Core/CM3/core_cm3.h ****
92:./lib/CMSIS/Core/CM3/core_cm3.h **** #ifndef __NVIC_PRIO_BITS
93:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
94:./lib/CMSIS/Core/CM3/core_cm3.h **** #endif
95:./lib/CMSIS/Core/CM3/core_cm3.h ****
96:./lib/CMSIS/Core/CM3/core_cm3.h ****
97:./lib/CMSIS/Core/CM3/core_cm3.h ****
98:./lib/CMSIS/Core/CM3/core_cm3.h ****
99:./lib/CMSIS/Core/CM3/core_cm3.h **** /**
100:./lib/CMSIS/Core/CM3/core_cm3.h **** * IO definitions
101:./lib/CMSIS/Core/CM3/core_cm3.h **** *
102:./lib/CMSIS/Core/CM3/core_cm3.h **** * define access restrictions to peripheral registers
103:./lib/CMSIS/Core/CM3/core_cm3.h **** */
104:./lib/CMSIS/Core/CM3/core_cm3.h ****
105:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __I volatile const /*!< defines 'read only' permissions */
106:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __O volatile /*!< defines 'write only' permissions */
107:./lib/CMSIS/Core/CM3/core_cm3.h **** #define __IO volatile /*!< defines 'read / write' permissions */
108:./lib/CMSIS/Core/CM3/core_cm3.h ****
109:./lib/CMSIS/Core/CM3/core_cm3.h ****
110:./lib/CMSIS/Core/CM3/core_cm3.h ****
111:./lib/CMSIS/Core/CM3/core_cm3.h **** /*******************************************************************************
112:./lib/CMSIS/Core/CM3/core_cm3.h **** * Register Abstraction
113:./lib/CMSIS/Core/CM3/core_cm3.h **** ******************************************************************************/
114:./lib/CMSIS/Core/CM3/core_cm3.h ****
115:./lib/CMSIS/Core/CM3/core_cm3.h ****
116:./lib/CMSIS/Core/CM3/core_cm3.h **** /* System Reset */
117:./lib/CMSIS/Core/CM3/core_cm3.h **** #define NVIC_VECTRESET 0 /*!< Vector Reset Bit */
118:./lib/CMSIS/Core/CM3/core_cm3.h **** #define NVIC_SYSRESETREQ 2 /*!< System Reset Request */
119:./lib/CMSIS/Core/CM3/core_cm3.h **** #define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */
120:./lib/CMSIS/Core/CM3/core_cm3.h **** #define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */
121:./lib/CMSIS/Core/CM3/core_cm3.h ****
122:./lib/CMSIS/Core/CM3/core_cm3.h **** /* Core Debug */
123:./lib/CMSIS/Core/CM3/core_cm3.h **** #define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */
124:./lib/CMSIS/Core/CM3/core_cm3.h **** #define ITM_TCR_ITMENA 1 /*!< ITM enable */
125:./lib/CMSIS/Core/CM3/core_cm3.h ****
126:./lib/CMSIS/Core/CM3/core_cm3.h ****
127:./lib/CMSIS/Core/CM3/core_cm3.h ****
128:./lib/CMSIS/Core/CM3/core_cm3.h ****
129:./lib/CMSIS/Core/CM3/core_cm3.h **** /* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
130:./lib/CMSIS/Core/CM3/core_cm3.h **** typedef struct
131:./lib/CMSIS/Core/CM3/core_cm3.h **** {
132:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */
133:./lib/CMSIS/Core/CM3/core_cm3.h **** uint32_t RESERVED0[24];
134:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */
135:./lib/CMSIS/Core/CM3/core_cm3.h **** uint32_t RSERVED1[24];
136:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */
137:./lib/CMSIS/Core/CM3/core_cm3.h **** uint32_t RESERVED2[24];
138:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */
139:./lib/CMSIS/Core/CM3/core_cm3.h **** uint32_t RESERVED3[24];
140:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */
141:./lib/CMSIS/Core/CM3/core_cm3.h **** uint32_t RESERVED4[56];
142:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */
143:./lib/CMSIS/Core/CM3/core_cm3.h **** uint32_t RESERVED5[644];
144:./lib/CMSIS/Core/CM3/core_cm3.h **** __O uint32_t STIR; /*!< Software Trigger Interrupt Register */
145:./lib/CMSIS/Core/CM3/core_cm3.h **** } NVIC_Type;
146:./lib/CMSIS/Core/CM3/core_cm3.h ****
147:./lib/CMSIS/Core/CM3/core_cm3.h ****
148:./lib/CMSIS/Core/CM3/core_cm3.h **** /* memory mapping struct for System Control Block */
149:./lib/CMSIS/Core/CM3/core_cm3.h **** typedef struct
150:./lib/CMSIS/Core/CM3/core_cm3.h **** {
151:./lib/CMSIS/Core/CM3/core_cm3.h **** __I uint32_t CPUID; /*!< CPU ID Base Register
152:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t ICSR; /*!< Interrupt Control State Register
153:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t VTOR; /*!< Vector Table Offset Register
154:./lib/CMSIS/Core/CM3/core_cm3.h **** __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register
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