📄 stm32f10x_fsmc.lst
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206:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
207:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_NORSRAMInitStruct->FSMC_WrapMode |
208:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
209:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
210:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
211:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
212:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
213:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
176 .loc 1 213 0
177 0036 0829 cmp r1, #8
178 .loc 1 201 0
179 0038 42F82530 str r3, [r2, r5, lsl #2]
180 .loc 1 213 0
181 003c 05D1 bne .L17
214:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** {
215:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
182 .loc 1 215 0
183 003e 52F82530 ldr r3, [r2, r5, lsl #2]
184 0042 43F04003 orr r3, r3, #64
185 0046 42F82530 str r3, [r2, r5, lsl #2]
186 .L17:
216:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** }
217:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** /* Bank1 NOR/SRAM timing register configuration */
218:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
187 .loc 1 218 0
188 004a 226B ldr r2, [r4, #48]
189 004c 681C adds r0, r5, #1
190 .LVL3:
191 004e 1168 ldr r1, [r2, #0]
192 0050 9369 ldr r3, [r2, #24]
193 0052 0B43 orrs r3, r3, r1
194 0054 5168 ldr r1, [r2, #4]
219:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
220:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
221:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
222:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16)
223:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
224:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
225:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
226:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c ****
227:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c ****
228:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
229:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
195 .loc 1 229 0
196 0056 B6F5804F cmp r6, #16384
197 .loc 1 218 0
198 005a 43EA0113 orr r3, r3, r1, lsl #4
199 005e 9168 ldr r1, [r2, #8]
200 0060 43EA0123 orr r3, r3, r1, lsl #8
201 0064 D168 ldr r1, [r2, #12]
202 0066 43EA0143 orr r3, r3, r1, lsl #16
203 006a 1169 ldr r1, [r2, #16]
204 006c 5269 ldr r2, [r2, #20]
205 006e 43EA0153 orr r3, r3, r1, lsl #20
206 0072 43EA0263 orr r3, r3, r2, lsl #24
207 0076 4FF02042 mov r2, #-1610612736
208 007a 42F82030 str r3, [r2, r0, lsl #2]
209 .loc 1 229 0
210 007e 13D1 bne .L18
230:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** {
231:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_Ad
232:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_Add
233:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSe
234:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision))
235:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLate
236:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMod
237:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
211 .loc 1 237 0
212 0080 616B ldr r1, [r4, #52]
213 0082 0A68 ldr r2, [r1, #0]
214 0084 8B69 ldr r3, [r1, #24]
215 0086 1343 orrs r3, r3, r2
216 0088 4A68 ldr r2, [r1, #4]
217 008a 43EA0213 orr r3, r3, r2, lsl #4
218 008e 8A68 ldr r2, [r1, #8]
219 0090 43EA0223 orr r3, r3, r2, lsl #8
220 0094 0A69 ldr r2, [r1, #16]
221 0096 43EA0253 orr r3, r3, r2, lsl #20
222 009a 4A69 ldr r2, [r1, #20]
223 009c 43EA0263 orr r3, r3, r2, lsl #24
224 00a0 044A ldr r2, .L21
225 00a2 42F82530 str r3, [r2, r5, lsl #2]
226 00a6 04E0 b .L20
227 .L18:
238:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
239:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
240:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
241:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
242:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
243:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
244:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** }
245:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** else
246:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** {
247:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
228 .loc 1 247 0
229 00a8 024B ldr r3, .L21
230 00aa 6FF07042 mvn r2, #-268435456
231 00ae 43F82520 str r2, [r3, r5, lsl #2]
232 .L20:
248:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** }
249:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** }
233 .loc 1 249 0
234 00b2 70BD pop {r4, r5, r6, pc}
235 .L22:
236 .align 2
237 .L21:
238 00b4 040100A0 .word -1610612476
239 .LFE29:
241 .section .text.FSMC_NANDInit,"ax",%progbits
242 .align 2
243 .global FSMC_NANDInit
244 .thumb
245 .thumb_func
247 FSMC_NANDInit:
248 .LFB30:
250:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c ****
251:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** /**
252:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** * @brief Initializes the FSMC NAND Banks according to the specified
253:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** * parameters in the FSMC_NANDInitStruct.
254:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
255:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** * structure that contains the configuration information for
256:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** * the FSMC NAND specified Banks.
257:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** * @retval : None
258:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** */
259:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
260:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** {
249 .loc 1 260 0
250 @ args = 0, pretend = 0, frame = 0
251 @ frame_needed = 0, uses_anonymous_args = 0
252 .LVL4:
261:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
262:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c ****
263:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** /* Check the parameters */
264:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
265:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
266:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param( IS_FSMC_DATA_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
267:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
268:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
269:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
270:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
271:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime
272:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupT
273:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupT
274:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTim
275:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupT
276:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSet
277:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSet
278:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetup
279:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c ****
280:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
281:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
253 .loc 1 281 0
254 0000 8268 ldr r2, [r0, #8]
255 0002 4368 ldr r3, [r0, #4]
256 .loc 1 260 0
257 0004 30B5 push {r4, r5, lr}
258 .LCFI1:
259 .loc 1 281 0
260 0006 1343 orrs r3, r3, r2
261 0008 C268 ldr r2, [r0, #12]
262 000a 43F00803 orr r3, r3, #8
263 000e 1343 orrs r3, r3, r2
264 0010 0269 ldr r2, [r0, #16]
282:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** PCR_MemoryType_NAND |
283:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
284:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_NANDInitStruct->FSMC_ECC |
285:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** FSMC_NANDInitStruct->FSMC_ECCPageSize |
286:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
287:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
288:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c ****
289:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
290:lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c **** tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
265 .loc 1 290 0
266 0012 C169 ldr r1, [r0, #28]
267 .loc 1 281 0
268 0014 1343 orrs r3, r3, r2
269 0016 4269 ldr r2, [r0, #20]
270 0018 43EA4223 orr r3, r3, r2, lsl #9
271 001c 8269 ldr r2, [r0, #24]
272 001e 43EA4235 orr r5, r3, r2, lsl #13
273 .LVL5:
274 .loc 1 290 0
275 0022 8B68 ldr r3, [r1, #8]
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