mycpu.map.eqn

Quantums 5.0开发环境

M2_87 = DFFEAS(M2L9, H1L3, CLRN, , , M2L7, , , 61);


--M2L2 is 8cpu:92|pc:65|74161:8|f74161:sub|9~COMBOUT
--operation mode is normal

M2L2 = U4L91 & (M2L4) # !U4L91 & U4L2;

--M2_9 is 8cpu:92|pc:65|74161:8|f74161:sub|9
--operation mode is normal

M2_9 = DFFEAS(M2L2, H1L3, CLRN, , , M2L5, , , 61);


--L1_q_a[7] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[7]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[7]_PORT_A_address_reg = DFFE(L1_q_a[7]_PORT_A_address, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_clock_0 = CLK;
L1_q_a[7]_PORT_A_data_out = MEMORY(, , L1_q_a[7]_PORT_A_address_reg, , , , , , L1_q_a[7]_clock_0, , , , , );
L1_q_a[7]_PORT_A_data_out_reg = DFFE(L1_q_a[7]_PORT_A_data_out, L1_q_a[7]_clock_0, , , );
L1_q_a[7] = L1_q_a[7]_PORT_A_data_out_reg[0];


--L1_q_a[6] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[6]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[6]_PORT_A_address_reg = DFFE(L1_q_a[6]_PORT_A_address, L1_q_a[6]_clock_0, , , );
L1_q_a[6]_clock_0 = CLK;
L1_q_a[6]_PORT_A_data_out = MEMORY(, , L1_q_a[6]_PORT_A_address_reg, , , , , , L1_q_a[6]_clock_0, , , , , );
L1_q_a[6]_PORT_A_data_out_reg = DFFE(L1_q_a[6]_PORT_A_data_out, L1_q_a[6]_clock_0, , , );
L1_q_a[6] = L1_q_a[6]_PORT_A_data_out_reg[0];


--L1_q_a[5] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[5]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[5]_PORT_A_address_reg = DFFE(L1_q_a[5]_PORT_A_address, L1_q_a[5]_clock_0, , , );
L1_q_a[5]_clock_0 = CLK;
L1_q_a[5]_PORT_A_data_out = MEMORY(, , L1_q_a[5]_PORT_A_address_reg, , , , , , L1_q_a[5]_clock_0, , , , , );
L1_q_a[5]_PORT_A_data_out_reg = DFFE(L1_q_a[5]_PORT_A_data_out, L1_q_a[5]_clock_0, , , );
L1_q_a[5] = L1_q_a[5]_PORT_A_data_out_reg[0];


--L1_q_a[4] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[4]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[4]_PORT_A_address_reg = DFFE(L1_q_a[4]_PORT_A_address, L1_q_a[4]_clock_0, , , );
L1_q_a[4]_clock_0 = CLK;
L1_q_a[4]_PORT_A_data_out = MEMORY(, , L1_q_a[4]_PORT_A_address_reg, , , , , , L1_q_a[4]_clock_0, , , , , );
L1_q_a[4]_PORT_A_data_out_reg = DFFE(L1_q_a[4]_PORT_A_data_out, L1_q_a[4]_clock_0, , , );
L1_q_a[4] = L1_q_a[4]_PORT_A_data_out_reg[0];


--L1_q_a[3] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[3]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[3]_PORT_A_address_reg = DFFE(L1_q_a[3]_PORT_A_address, L1_q_a[3]_clock_0, , , );
L1_q_a[3]_clock_0 = CLK;
L1_q_a[3]_PORT_A_data_out = MEMORY(, , L1_q_a[3]_PORT_A_address_reg, , , , , , L1_q_a[3]_clock_0, , , , , );
L1_q_a[3]_PORT_A_data_out_reg = DFFE(L1_q_a[3]_PORT_A_data_out, L1_q_a[3]_clock_0, , , );
L1_q_a[3] = L1_q_a[3]_PORT_A_data_out_reg[0];


--L1_q_a[2] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[2]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[2]_PORT_A_address_reg = DFFE(L1_q_a[2]_PORT_A_address, L1_q_a[2]_clock_0, , , );
L1_q_a[2]_clock_0 = CLK;
L1_q_a[2]_PORT_A_data_out = MEMORY(, , L1_q_a[2]_PORT_A_address_reg, , , , , , L1_q_a[2]_clock_0, , , , , );
L1_q_a[2]_PORT_A_data_out_reg = DFFE(L1_q_a[2]_PORT_A_data_out, L1_q_a[2]_clock_0, , , );
L1_q_a[2] = L1_q_a[2]_PORT_A_data_out_reg[0];


--L1_q_a[1] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[1]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[1]_PORT_A_address_reg = DFFE(L1_q_a[1]_PORT_A_address, L1_q_a[1]_clock_0, , , );
L1_q_a[1]_clock_0 = CLK;
L1_q_a[1]_PORT_A_data_out = MEMORY(, , L1_q_a[1]_PORT_A_address_reg, , , , , , L1_q_a[1]_clock_0, , , , , );
L1_q_a[1]_PORT_A_data_out_reg = DFFE(L1_q_a[1]_PORT_A_data_out, L1_q_a[1]_clock_0, , , );
L1_q_a[1] = L1_q_a[1]_PORT_A_data_out_reg[0];


--L1_q_a[0] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[0]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[0]_PORT_A_address_reg = DFFE(L1_q_a[0]_PORT_A_address, L1_q_a[0]_clock_0, , , );
L1_q_a[0]_clock_0 = CLK;
L1_q_a[0]_PORT_A_data_out = MEMORY(, , L1_q_a[0]_PORT_A_address_reg, , , , , , L1_q_a[0]_clock_0, , , , , );
L1_q_a[0]_PORT_A_data_out_reg = DFFE(L1_q_a[0]_PORT_A_data_out, L1_q_a[0]_clock_0, , , );
L1_q_a[0] = L1_q_a[0]_PORT_A_data_out_reg[0];


--L1_q_a[15] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[15]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[15]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[15]_PORT_A_address_reg = DFFE(L1_q_a[15]_PORT_A_address, L1_q_a[15]_clock_0, , , );
L1_q_a[15]_clock_0 = CLK;
L1_q_a[15]_PORT_A_data_out = MEMORY(, , L1_q_a[15]_PORT_A_address_reg, , , , , , L1_q_a[15]_clock_0, , , , , );
L1_q_a[15]_PORT_A_data_out_reg = DFFE(L1_q_a[15]_PORT_A_data_out, L1_q_a[15]_clock_0, , , );
L1_q_a[15] = L1_q_a[15]_PORT_A_data_out_reg[0];


--L1_q_a[14] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[14]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[14]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[14]_PORT_A_address_reg = DFFE(L1_q_a[14]_PORT_A_address, L1_q_a[14]_clock_0, , , );
L1_q_a[14]_clock_0 = CLK;
L1_q_a[14]_PORT_A_data_out = MEMORY(, , L1_q_a[14]_PORT_A_address_reg, , , , , , L1_q_a[14]_clock_0, , , , , );
L1_q_a[14]_PORT_A_data_out_reg = DFFE(L1_q_a[14]_PORT_A_data_out, L1_q_a[14]_clock_0, , , );
L1_q_a[14] = L1_q_a[14]_PORT_A_data_out_reg[0];


--L1_q_a[12] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[12]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[12]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[12]_PORT_A_address_reg = DFFE(L1_q_a[12]_PORT_A_address, L1_q_a[12]_clock_0, , , );
L1_q_a[12]_clock_0 = CLK;
L1_q_a[12]_PORT_A_data_out = MEMORY(, , L1_q_a[12]_PORT_A_address_reg, , , , , , L1_q_a[12]_clock_0, , , , , );
L1_q_a[12]_PORT_A_data_out_reg = DFFE(L1_q_a[12]_PORT_A_data_out, L1_q_a[12]_clock_0, , , );
L1_q_a[12] = L1_q_a[12]_PORT_A_data_out_reg[0];


--L1_q_a[11] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[11]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[11]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[11]_PORT_A_address_reg = DFFE(L1_q_a[11]_PORT_A_address, L1_q_a[11]_clock_0, , , );
L1_q_a[11]_clock_0 = CLK;
L1_q_a[11]_PORT_A_data_out = MEMORY(, , L1_q_a[11]_PORT_A_address_reg, , , , , , L1_q_a[11]_clock_0, , , , , );
L1_q_a[11]_PORT_A_data_out_reg = DFFE(L1_q_a[11]_PORT_A_data_out, L1_q_a[11]_clock_0, , , );
L1_q_a[11] = L1_q_a[11]_PORT_A_data_out_reg[0];


--L1_q_a[10] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[10]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[10]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[10]_PORT_A_address_reg = DFFE(L1_q_a[10]_PORT_A_address, L1_q_a[10]_clock_0, , , );
L1_q_a[10]_clock_0 = CLK;
L1_q_a[10]_PORT_A_data_out = MEMORY(, , L1_q_a[10]_PORT_A_address_reg, , , , , , L1_q_a[10]_clock_0, , , , , );
L1_q_a[10]_PORT_A_data_out_reg = DFFE(L1_q_a[10]_PORT_A_data_out, L1_q_a[10]_clock_0, , , );
L1_q_a[10] = L1_q_a[10]_PORT_A_data_out_reg[0];


--L1_q_a[9] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[9]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[9]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[9]_PORT_A_address_reg = DFFE(L1_q_a[9]_PORT_A_address, L1_q_a[9]_clock_0, , , );
L1_q_a[9]_clock_0 = CLK;
L1_q_a[9]_PORT_A_data_out = MEMORY(, , L1_q_a[9]_PORT_A_address_reg, , , , , , L1_q_a[9]_clock_0, , , , , );
L1_q_a[9]_PORT_A_data_out_reg = DFFE(L1_q_a[9]_PORT_A_data_out, L1_q_a[9]_clock_0, , , );
L1_q_a[9] = L1_q_a[9]_PORT_A_data_out_reg[0];


--L1_q_a[8] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[8]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[8]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[8]_PORT_A_address_reg = DFFE(L1_q_a[8]_PORT_A_address, L1_q_a[8]_clock_0, , , );
L1_q_a[8]_clock_0 = CLK;
L1_q_a[8]_PORT_A_data_out = MEMORY(, , L1_q_a[8]_PORT_A_address_reg, , , , , , L1_q_a[8]_clock_0, , , , , );
L1_q_a[8]_PORT_A_data_out_reg = DFFE(L1_q_a[8]_PORT_A_data_out, L1_q_a[8]_clock_0, , , );
L1_q_a[8] = L1_q_a[8]_PORT_A_data_out_reg[0];


--L1_q_a[22] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[22]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[22]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[22]_PORT_A_address_reg = DFFE(L1_q_a[22]_PORT_A_address, L1_q_a[22]_clock_0, , , );
L1_q_a[22]_clock_0 = CLK;
L1_q_a[22]_PORT_A_data_out = MEMORY(, , L1_q_a[22]_PORT_A_address_reg, , , , , , L1_q_a[22]_clock_0, , , , , );
L1_q_a[22]_PORT_A_data_out_reg = DFFE(L1_q_a[22]_PORT_A_data_out, L1_q_a[22]_clock_0, , , );
L1_q_a[22] = L1_q_a[22]_PORT_A_data_out_reg[0];


--L1_q_a[21] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[21]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[21]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[21]_PORT_A_address_reg = DFFE(L1_q_a[21]_PORT_A_address, L1_q_a[21]_clock_0, , , );
L1_q_a[21]_clock_0 = CLK;
L1_q_a[21]_PORT_A_data_out = MEMORY(, , L1_q_a[21]_PORT_A_address_reg, , , , , , L1_q_a[21]_clock_0, , , , , );
L1_q_a[21]_PORT_A_data_out_reg = DFFE(L1_q_a[21]_PORT_A_data_out, L1_q_a[21]_clock_0, , , );
L1_q_a[21] = L1_q_a[21]_PORT_A_data_out_reg[0];


--L1_q_a[20] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[20]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[20]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[20]_PORT_A_address_reg = DFFE(L1_q_a[20]_PORT_A_address, L1_q_a[20]_clock_0, , , );
L1_q_a[20]_clock_0 = CLK;
L1_q_a[20]_PORT_A_data_out = MEMORY(, , L1_q_a[20]_PORT_A_address_reg, , , , , , L1_q_a[20]_clock_0, , , , , );
L1_q_a[20]_PORT_A_data_out_reg = DFFE(L1_q_a[20]_PORT_A_data_out, L1_q_a[20]_clock_0, , , );
L1_q_a[20] = L1_q_a[20]_PORT_A_data_out_reg[0];


--L1_q_a[19] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[19]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[19]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[19]_PORT_A_address_reg = DFFE(L1_q_a[19]_PORT_A_address, L1_q_a[19]_clock_0, , , );
L1_q_a[19]_clock_0 = CLK;
L1_q_a[19]_PORT_A_data_out = MEMORY(, , L1_q_a[19]_PORT_A_address_reg, , , , , , L1_q_a[19]_clock_0, , , , , );
L1_q_a[19]_PORT_A_data_out_reg = DFFE(L1_q_a[19]_PORT_A_data_out, L1_q_a[19]_clock_0, , , );
L1_q_a[19] = L1_q_a[19]_PORT_A_data_out_reg[0];


--L1_q_a[18] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[18]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[18]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[18]_PORT_A_address_reg = DFFE(L1_q_a[18]_PORT_A_address, L1_q_a[18]_clock_0, , , );
L1_q_a[18]_clock_0 = CLK;
L1_q_a[18]_PORT_A_data_out = MEMORY(, , L1_q_a[18]_PORT_A_address_reg, , , , , , L1_q_a[18]_clock_0, , , , , );
L1_q_a[18]_PORT_A_data_out_reg = DFFE(L1_q_a[18]_PORT_A_data_out, L1_q_a[18]_clock_0, , , );
L1_q_a[18] = L1_q_a[18]_PORT_A_data_out_reg[0];


--L1_q_a[17] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[17]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[17]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[17]_PORT_A_address_reg = DFFE(L1_q_a[17]_PORT_A_address, L1_q_a[17]_clock_0, , , );
L1_q_a[17]_clock_0 = CLK;
L1_q_a[17]_PORT_A_data_out = MEMORY(, , L1_q_a[17]_PORT_A_address_reg, , , , , , L1_q_a[17]_clock_0, , , , , );
L1_q_a[17]_PORT_A_data_out_reg = DFFE(L1_q_a[17]_PORT_A_data_out, L1_q_a[17]_clock_0, , , );
L1_q_a[17] = L1_q_a[17]_PORT_A_data_out_reg[0];


--L1_q_a[16] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[16]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[16]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[16]_PORT_A_address_reg = DFFE(L1_q_a[16]_PORT_A_address, L1_q_a[16]_clock_0, , , );
L1_q_a[16]_clock_0 = CLK;
L1_q_a[16]_PORT_A_data_out = MEMORY(, , L1_q_a[16]_PORT_A_address_reg, , , , , , L1_q_a[16]_clock_0, , , , , );
L1_q_a[16]_PORT_A_data_out_reg = DFFE(L1_q_a[16]_PORT_A_data_out, L1_q_a[16]_clock_0, , , );
L1_q_a[16] = L1_q_a[16]_PORT_A_data_out_reg[0];


--B8_12 is 8cpu:92|alu:62|74273b:5|12
--operation mode is normal

B8_12_lut_out = M3L81;
B8_12 = DFFEAS(B8_12_lut_out, P1_21, VCC, , , , , , );


--B7_12 is 8cpu:92|alu:62|74273b:4|12
--operation mode is normal

B7_12_lut_out = M3L81;
B7_12 = DFFEAS(B7_12_lut_out, P1_18, VCC, , , , , , );


--Y3L4 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~161
--operation mode is arithmetic

Y3L4_carry_eqn = Y3L7;
Y3L4 = B8_13 $ B7_13 $ !Y3L4_carry_eqn;

--Y3L5 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~163
--operation mode is arithmetic

Y3L5 = CARRY(B8_13 & (B7_13 # !Y3L7) # !B8_13 & B7_13 & !Y3L7);


--A1L21 is 91~40
--operation mode is normal

A1L21 = B4_12 & K3;


--A1L31 is 91~41
--operation mode is normal

A1L31 = J1_35 & (B4_13 # A1L21) # !CLRN;


--M1_9 is 74161:12|f74161:sub|9
--operation mode is arithmetic

M1_9_lut_out = !M1_9;
M1_9 = DFFEAS(M1_9_lut_out, 17, !97, , , , , , );

--M1_81 is 74161:12|f74161:sub|81
--operation mode is arithmetic

M1_81 = CARRY(M1_9);


--M1_87 is 74161:12|f74161:sub|87
--operation mode is arithmetic

M1_87_carry_eqn = M1_81;
M1_87_lut_out = M1_87 $ (M1_87_carry_eqn);
M1_87 = DFFEAS(M1_87_lut_out, 17, !97, , , , , , );

--M1_85 is 74161:12|f74161:sub|85
--operation mode is arithmetic

M1_85 = CARRY(!M1_81 # !M1_87);


--M1_99 is 74161:12|f74161:sub|99
--operation mode is arithmetic

M1_99_carry_eqn = M1_85;
M1_99_lut_out = M1_99 $ (!M1_99_carry_eqn);
M1_99 = DFFEAS(M1_99_lut_out, 17, !97, , , , , , );

--M1_95 is 74161:12|f74161:sub|95
--operation mode is arithmetic

M1_95 = CARRY(M1_99 & (!M1_85));


--M1_110 is 74161:12|f74161:sub|110
--operation mode is normal

M1_110_carry_eqn = M1_95;
M1_110_lut_out = M1_110_carry_eqn $ M1_110;
M1_110 = DFFEAS(M1_110_lut_out, 17, !97, , , , , , );


--B3_15 is 74273b:10|15
--operation mode is normal

B3_15_lut_out = M3L2;
B3_15 = DFFEAS(B3_15_lut_out, 19, !76, , , , , , );


--B3_14 is 74273b:10|14
--operation mode is normal

B3_14_lut_out = M3L11;
B3_14 = DFFEAS(B3_14_lut_out, 19, !76, , , , , , );


--B3_13 is 74273b:10|13
--operation mode is normal

B3_13_lut_out = M3L51;
B3_13 = DFFEAS(B3_13_lut_out, 19, !76, , , , , , );


--24 is 24
--operation mode is normal

24 = B3_13 # K2;


--B3_12 is 74273b:10|12
--operation mode is normal

B3_12_lut_out = M3L81;
B3_12 = DFFEAS(B3_12_lut_out, 19, !76, , , , , , );


--25 is 25
--operation mode is normal

25 = B3_12 # K1;


--61 is 61
--operation mode is normal

61 = !B2_19 # !J1L2;


--H1L3 is 8cpu:92|59~44
--operation mode is normal

H1L3 = CLK & (J1_35 & B2_13 # !61);


--B3_19 is 74273b:10|19
--operation mode is normal

B3_19_lut_out = M2L2;
B3_19 = DFFEAS(B3_19_lut_out, 19, !76, , , , , , );