mycpu.hif

Quantums 5.0开发环境

ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
A
B
C
CLK
CLRN
D
ENP
ENT
LDN
QA
QB
QC
QD
RCO
}
# include_file {
..|quartus|libraries|megafunctions|aglobal.inc
1114012420
}
# hierarchies {
8cpu:92|pc:65|74161:8
}
# end
# entity
f74161
# case_insensitive
# source_file
..|quartus|libraries|others|maxplus2|f74161.bdf
1107578552
23
# storage
db|mycpu.(20).cnf
db|mycpu.(20).cnf
# hierarchies {
8cpu:92|pc:65|74161:8|f74161:sub
8cpu:92|pc:65|74161:9|f74161:sub
74161:12|f74161:sub
}
# end
# entity
74161
# case_insensitive
# source_file
..|quartus|libraries|others|maxplus2|74161.tdf
1107570978
6
# storage
db|mycpu.(21).cnf
db|mycpu.(21).cnf
# user_parameter {
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
A
B
C
CLK
CLRN
D
ENP
ENT
LDN
QA
QB
QC
QD
}
# include_file {
..|quartus|libraries|megafunctions|aglobal.inc
1114012420
}
# hierarchies {
8cpu:92|pc:65|74161:9
}
# end
# entity
sequence
# case_insensitive
# source_file
sequence.bdf
1195054626
23
# storage
db|mycpu.(22).cnf
db|mycpu.(22).cnf
# hierarchies {
sequence:103
}
# end
# entity
74393b
# case_insensitive
# source_file
74393b.bdf
978492424
23
# storage
db|mycpu.(23).cnf
db|mycpu.(23).cnf
# hierarchies {
sequence:103|74393b:25
}
# end
# entity
dcf
# case_insensitive
# source_file
dcf.bdf
979185130
23
# storage
db|mycpu.(24).cnf
db|mycpu.(24).cnf
# hierarchies {
dcf:84
}
# end
# entity
1to8
# case_insensitive
# source_file
1to8.bdf
977104738
23
# storage
db|mycpu.(25).cnf
db|mycpu.(25).cnf
# hierarchies {
1to8:43
1to8:42
1to8:32
1to8:41
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|quartus|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|mycpu.(27).cnf
db|mycpu.(27).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
24
PARAMETER_UNKNOWN
USR
WIDTHAD_A
8
PARAMETER_UNKNOWN
USR
NUMWORDS_A
256
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
D:/ourcpu/lpm_myrom.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_b7r
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a16
q_a17
q_a18
q_a19
q_a20
q_a21
q_a22
q_a23
}
# include_file {
..|quartus|libraries|megafunctions|aglobal50.inc
1114012420
..|quartus|libraries|megafunctions|lpm_mux.inc
1107574776
..|quartus|libraries|megafunctions|altsyncram.inc
1107573506
..|quartus|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|quartus|libraries|megafunctions|lpm_decode.inc
1107574570
..|quartus|libraries|megafunctions|a_rdenreg.inc
1107572148
..|quartus|libraries|megafunctions|altrom.inc
1107573422
..|quartus|libraries|megafunctions|altram.inc
1107573384
..|quartus|libraries|megafunctions|altdpram.inc
1107573082
..|quartus|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
lpm_rom0:7|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_b7r
# case_insensitive
# source_file
db|altsyncram_b7r.tdf
1195055703
6
# storage
db|mycpu.(28).cnf
db|mycpu.(28).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a16
q_a17
q_a18
q_a19
q_a20
q_a21
q_a22
q_a23
}
# memory_file {
D:|ourcpu|lpm_myrom.mif
1195578095
}
# hierarchies {
lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated
}
# end
# entity
8to1
# case_insensitive
# source_file
8to1.bdf
977450846
23
# storage
db|mycpu.(29).cnf
db|mycpu.(29).cnf
# hierarchies {
8to1:22
}
# end
# entity
74161
# case_insensitive
# source_file
..|quartus|libraries|others|maxplus2|74161.tdf
1107570978
6
# storage
db|mycpu.(30).cnf
db|mycpu.(30).cnf
# user_parameter {
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
CLK
CLRN
ENP
ENT
LDN
QA
QB
QC
QD
}
# include_file {
..|quartus|libraries|megafunctions|aglobal.inc
1114012420
}
# hierarchies {
74161:12
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|quartus|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|mycpu.(31).cnf
db|mycpu.(31).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
SINGLE_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_UNKNOWN
USR
WIDTHAD_A
8
PARAMETER_UNKNOWN
USR
NUMWORDS_A
256
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
D:/tanjing/myspu/ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_td41
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# include_file {
..|quartus|libraries|megafunctions|aglobal50.inc
1114012420
..|quartus|libraries|megafunctions|lpm_mux.inc
1107574776
..|quartus|libraries|megafunctions|altsyncram.inc
1107573506
..|quartus|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|quartus|libraries|megafunctions|lpm_decode.inc
1107574570
..|quartus|libraries|megafunctions|a_rdenreg.inc
1107572148
..|quartus|libraries|megafunctions|altrom.inc
1107573422
..|quartus|libraries|megafunctions|altram.inc
1107573384
..|quartus|libraries|megafunctions|altdpram.inc
1107573082
..|quartus|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component
}
# end
# entity
cpu001
# case_insensitive
# source_file
cpu001.bdf
1195580077
23
# storage
db|mycpu.(0).cnf
db|mycpu.(0).cnf
# hierarchies {
|
}
# end
# entity
8cpu
# case_insensitive
# source_file
8cpu.bdf
1195580078
23
# storage
db|mycpu.(1).cnf
db|mycpu.(1).cnf
# hierarchies {
8cpu:92
}
# end
# entity
lpm_ram_dq0
# case_insensitive
# source_file
lpm_ram_dq0.tdf
1195580064
6
# storage
db|mycpu.(13).cnf
db|mycpu.(13).cnf
# used_port {
address0
address1
address2
address3
address4
address5
address6
address7
clock
data0
data1
data2
data3
data4
data5
data6
data7
q0
q1
q2
q3
q4
q5
q6
q7
wren
}
# include_file {
..|quartus|libraries|megafunctions|altsyncram.inc
1107573506
}
# hierarchies {
8cpu:92|lpm_ram_dq0:inst
}
# end
# entity
altsyncram_td41
# case_insensitive
# source_file
db|altsyncram_td41.tdf
1195578528
6
# storage
db|mycpu.(26).cnf
db|mycpu.(26).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# memory_file {
D:|tanjing|myspu|ram.mif
1195580046
}
# hierarchies {
8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated
}
# end
# entity
lpm_rom0
# case_insensitive
# source_file
lpm_rom0.tdf
1195578998
6
# storage
db|mycpu.(32).cnf
db|mycpu.(32).cnf
# used_port {
address0
address1
address2
address3
address4
address5
address6
address7
clock
q0
q10
q11
q12
q13
q14
q15
q16
q17
q18
q19
q1
q20
q21
q22
q23
q2
q3
q4
q5
q6
q7
q8
q9
}
# include_file {
..|quartus|libraries|megafunctions|altsyncram.inc
1107573506
}
# hierarchies {
lpm_rom0:7
}
# end
# complete