mycpu.hif

Quantums 5.0开发环境

Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1614
OFF
OFF
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VRSM_ON
VHSM_ON
0
# entity
alu
# case_insensitive
# source_file
alu.bdf
978061792
23
# storage
db|mycpu.(2).cnf
db|mycpu.(2).cnf
# hierarchies {
8cpu:92|alu:62
}
# end
# entity
lpm_add_sub
# case_insensitive
# source_file
..|quartus|libraries|megafunctions|LPM_ADD_SUB.tdf
1114012446
6
# storage
db|mycpu.(3).cnf
db|mycpu.(3).cnf
# user_parameter {
LPM_WIDTH
8
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
DEF
LPM_PIPELINE
0
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_4pg
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
cin
cout
dataa0
dataa1
dataa2
dataa3
dataa4
dataa5
dataa6
dataa7
datab0
datab1
datab2
datab3
datab4
datab5
datab6
datab7
result0
result1
result2
result3
result4
result5
result6
result7
}
# include_file {
..|quartus|libraries|megafunctions|addcore.inc
1107572218
..|quartus|libraries|megafunctions|look_add.inc
1107574364
..|quartus|libraries|megafunctions|bypassff.inc
1107573920
..|quartus|libraries|megafunctions|altshift.inc
1107573438
..|quartus|libraries|megafunctions|alt_stratix_add_sub.inc
1107572606
..|quartus|libraries|megafunctions|alt_mercury_add_sub.inc
1107572592
..|quartus|libraries|megafunctions|aglobal50.inc
1114012420
}
# hierarchies {
8cpu:92|alu:62|lpm_add_sub:1
}
# end
# entity
addcore
# case_insensitive
# source_file
..|quartus|libraries|megafunctions|addcore.tdf
1114012446
6
# storage
db|mycpu.(4).cnf
db|mycpu.(4).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
width
8
PARAMETER_UNKNOWN
USR
REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
USR
DIRECTION
ADD
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
dataa0
dataa1
dataa2
dataa3
dataa4
dataa5
dataa6
dataa7
datab0
datab1
datab2
datab3
datab4
datab5
datab6
datab7
cin
result0
result1
result2
result3
result4
result5
result6
result7
cout
}
# include_file {
..|quartus|libraries|megafunctions|addcore.inc
1107572218
..|quartus|libraries|megafunctions|aglobal50.inc
1114012420
..|quartus|libraries|megafunctions|a_csnbuffer.inc
1107571892
}
# hierarchies {
8cpu:92|alu:62|lpm_add_sub:1|addcore:adder
}
# end
# entity
a_csnbuffer
# case_insensitive
# source_file
..|quartus|libraries|megafunctions|a_csnbuffer.tdf
1114012448
6
# storage
db|mycpu.(5).cnf
db|mycpu.(5).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
NEED_CARRY
0
PARAMETER_UNKNOWN
DEF
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sin0
sout0
}
# hierarchies {
8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:oflow_node
8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:cout_node
}
# end
# entity
a_csnbuffer
# case_insensitive
# source_file
..|quartus|libraries|megafunctions|a_csnbuffer.tdf
1114012448
6
# storage
db|mycpu.(6).cnf
db|mycpu.(6).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
NEED_CARRY
1
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sin0
sin1
sin2
sin3
sin4
sin5
sin6
sin7
cin0
cin1
cin2
cin3
cin4
cin5
cin6
cin7
sout0
sout1
sout2
sout3
sout4
sout5
sout6
sout7
cout0
cout1
cout2
cout3
cout4
cout5
cout6
cout7
}
# hierarchies {
8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node
}
# end
# entity
altshift
# case_insensitive
# source_file
..|quartus|libraries|megafunctions|altshift.tdf
1114012454
6
# storage
db|mycpu.(7).cnf
db|mycpu.(7).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
result0
result1
result2
result3
result4
result5
result6
result7
}
# hierarchies {
8cpu:92|alu:62|lpm_add_sub:1|altshift:result_ext_latency_ffs
}
# end
# entity
altshift
# case_insensitive
# source_file
..|quartus|libraries|megafunctions|altshift.tdf
1114012454
6
# storage
db|mycpu.(8).cnf
db|mycpu.(8).cnf
# user_parameter {
WIDTH
1
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
result0
}
# hierarchies {
8cpu:92|alu:62|lpm_add_sub:1|altshift:carry_ext_latency_ffs
8cpu:92|alu:62|lpm_add_sub:1|altshift:oflow_ext_latency_ffs
}
# end
# entity
74273b
# case_insensitive
# source_file
..|quartus|libraries|others|maxplus2|74273b.bdf
1107572830
23
# storage
db|mycpu.(9).cnf
db|mycpu.(9).cnf
# hierarchies {
8cpu:92|alu:62|74273b:4
8cpu:92|alu:62|74273b:5
8cpu:92|alu:62|74273b:11
8cpu:92|74273b:3
8cpu:92|74273b:7
74273b:21
74273b:3
74273b:10
74273b:2
}
# end
# entity
busmux
# case_insensitive
# source_file
..|quartus|libraries|megafunctions|BUSMUX.tdf
1114012436
6
# storage
db|mycpu.(10).cnf
db|mycpu.(10).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
}
# used_port {
dataa0
dataa1
dataa2
dataa3
dataa4
dataa5
dataa6
dataa7
datab0
datab1
datab2
datab3
datab4
datab5
datab6
datab7
result0
result1
result2
result3
result4
result5
result6
result7
sel
}
# include_file {
..|quartus|libraries|megafunctions|lpm_mux.inc
1107574776
}
# hierarchies {
8cpu:92|busmux:49
8cpu:92|busmux:33
8cpu:92|busmux:31
8cpu:92|busmux:48
}
# end
# entity
lpm_mux
# case_insensitive
# source_file
..|quartus|libraries|megafunctions|lpm_mux.tdf
1114012454
6
# storage
db|mycpu.(11).cnf
db|mycpu.(11).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
8
PARAMETER_UNKNOWN
USR
LPM_SIZE
2
PARAMETER_UNKNOWN
USR
LPM_WIDTHS
1
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mux_afc
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
data0_0
data0_1
data0_2
data0_3
data0_4
data0_5
data0_6
data0_7
data1_0
data1_1
data1_2
data1_3
data1_4
data1_5
data1_6
data1_7
sel0
result0
result1
result2
result3
result4
result5
result6
result7
}
# include_file {
..|quartus|libraries|megafunctions|bypassff.inc
1107573920
..|quartus|libraries|megafunctions|altshift.inc
1107573438
..|quartus|libraries|megafunctions|aglobal50.inc
1114012420
..|quartus|libraries|megafunctions|muxlut.inc
1107575250
}
# hierarchies {
8cpu:92|busmux:49|lpm_mux:$00000
8cpu:92|busmux:33|lpm_mux:$00000
8cpu:92|busmux:31|lpm_mux:$00000
8cpu:92|busmux:48|lpm_mux:$00000
}
# end
# entity
mux_afc
# case_insensitive
# source_file
db|mux_afc.tdf
1195055124
6
# storage
db|mycpu.(12).cnf
db|mycpu.(12).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
sel0
result0
result1
result2
result3
result4
result5
result6
result7
}
# hierarchies {
8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated
8cpu:92|busmux:33|lpm_mux:$00000|mux_afc:auto_generated
8cpu:92|busmux:31|lpm_mux:$00000|mux_afc:auto_generated
8cpu:92|busmux:48|lpm_mux:$00000|mux_afc:auto_generated
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|quartus|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|mycpu.(14).cnf
db|mycpu.(14).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
SINGLE_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_UNKNOWN
USR
WIDTHAD_A
8
PARAMETER_UNKNOWN
USR
NUMWORDS_A
256
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_9r21
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# include_file {
..|quartus|libraries|megafunctions|aglobal50.inc
1114012420
..|quartus|libraries|megafunctions|lpm_mux.inc
1107574776
..|quartus|libraries|megafunctions|altsyncram.inc
1107573506
..|quartus|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|quartus|libraries|megafunctions|lpm_decode.inc
1107574570
..|quartus|libraries|megafunctions|a_rdenreg.inc
1107572148
..|quartus|libraries|megafunctions|altrom.inc
1107573422
..|quartus|libraries|megafunctions|altram.inc
1107573384
..|quartus|libraries|megafunctions|altdpram.inc
1107573082
..|quartus|libraries|megafunctions|altqpram.inc
1107573362
}
# end
# entity
altsyncram_9r21
# case_insensitive
# source_file
db|altsyncram_9r21.tdf
1195055125
6
# storage
db|mycpu.(15).cnf
db|mycpu.(15).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# memory_file {
ram.mif
965013654
}
# end
# entity
bi74670
# case_insensitive
# source_file
bi74670.bdf
982031518
23
# storage
db|mycpu.(16).cnf
db|mycpu.(16).cnf
# hierarchies {
8cpu:92|bi74670:67
}
# end
# entity
74670c
# case_insensitive
# source_file
74670c.bdf
977902370
23
# storage
db|mycpu.(17).cnf
db|mycpu.(17).cnf
# hierarchies {
8cpu:92|bi74670:67|74670c:34
8cpu:92|bi74670:67|74670c:32
}
# end
# entity
pc
# case_insensitive
# source_file
pc.bdf
982031104
23
# storage
db|mycpu.(18).cnf
db|mycpu.(18).cnf
# hierarchies {
8cpu:92|pc:65
}
# end
# entity
74161
# case_insensitive
# source_file
..|quartus|libraries|others|maxplus2|74161.tdf
1107570978
6
# storage
db|mycpu.(19).cnf
db|mycpu.(19).cnf
# user_parameter {
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS