mycpu.tan.rpt

Quantums 5.0开发环境

; Worst-case th                ; N/A                                      ; None          ; 11.248 ns                        ; kdata[8]                    ; 8cpu:92|pc:65|74161:9|f74161:sub|110                                                                                   ;            ; CLK      ; 0            ;
; Clock Setup: 'CLK'           ; N/A                                      ; None          ; 35.48 MHz ( period = 28.184 ns ) ; sequence:103|74393b:25|3    ; 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|ram_block1a7~porta_datain_reg1 ; CLK        ; CLK      ; 0            ;
; Clock Hold: 'CLK'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; 8cpu:92|alu:62|74273b:11|17 ; 8cpu:92|pc:65|74161:8|f74161:sub|99                                                                                    ; CLK        ; CLK      ; 860          ;
; Total number of failed paths ;                                          ;               ;                                  ;                             ;                                                                                                                        ;            ;          ; 860          ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------+------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                        ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------+------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                 ; To                                                                                                                     ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------+------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 35.48 MHz ( period = 28.184 ns )                    ; sequence:103|74393b:25|3             ; 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|ram_block1a7~porta_datain_reg1 ; CLK        ; CLK      ; None                        ; None                      ; 13.793 ns               ;
; N/A                                     ; 35.71 MHz ( period = 28.002 ns )                    ; sequence:103|74393b:25|1             ; 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|ram_block1a7~porta_datain_reg1 ; CLK        ; CLK      ; None                        ; None                      ; 13.702 ns               ;
; N/A                                     ; 36.04 MHz ( period = 27.744 ns )                    ; sequence:103|74393b:25|9             ; 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|ram_block1a7~porta_datain_reg1 ; CLK        ; CLK      ; None                        ; None                      ; 13.573 ns               ;