mycpu.fit.eqn

来自「Quantums 5.0开发环境」· EQN 代码 · 共 1,973 行 · 第 1/5 页

--Port A Input: Registered, Port A Output: Registered
AB1_q_a[7]_PORT_A_data_in = BUS(M3L22, M3L91, M3L41, M3L2, M2L12, M2L61, M2L11, M2L2);
AB1_q_a[7]_PORT_A_data_in_reg = DFFE(AB1_q_a[7]_PORT_A_data_in, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[7]_PORT_A_address_reg = DFFE(AB1_q_a[7]_PORT_A_address, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_write_enable = 70;
AB1_q_a[7]_PORT_A_write_enable_reg = DFFE(AB1_q_a[7]_PORT_A_write_enable, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_clock_0 = GLOBAL(CLK);
AB1_q_a[7]_PORT_A_data_out = MEMORY(AB1_q_a[7]_PORT_A_data_in_reg, , AB1_q_a[7]_PORT_A_address_reg, , AB1_q_a[7]_PORT_A_write_enable_reg, , , , AB1_q_a[7]_clock_0, , , , , );
AB1_q_a[7]_PORT_A_data_out_reg = DFFE(AB1_q_a[7]_PORT_A_data_out, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7] = AB1_q_a[7]_PORT_A_data_out_reg[0];

--AB1_q_a[0] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|q_a[0] at M4K_X17_Y7
AB1_q_a[7]_PORT_A_data_in = BUS(M3L22, M3L91, M3L41, M3L2, M2L12, M2L61, M2L11, M2L2);
AB1_q_a[7]_PORT_A_data_in_reg = DFFE(AB1_q_a[7]_PORT_A_data_in, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[7]_PORT_A_address_reg = DFFE(AB1_q_a[7]_PORT_A_address, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_write_enable = 70;
AB1_q_a[7]_PORT_A_write_enable_reg = DFFE(AB1_q_a[7]_PORT_A_write_enable, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_clock_0 = GLOBAL(CLK);
AB1_q_a[7]_PORT_A_data_out = MEMORY(AB1_q_a[7]_PORT_A_data_in_reg, , AB1_q_a[7]_PORT_A_address_reg, , AB1_q_a[7]_PORT_A_write_enable_reg, , , , AB1_q_a[7]_clock_0, , , , , );
AB1_q_a[7]_PORT_A_data_out_reg = DFFE(AB1_q_a[7]_PORT_A_data_out, AB1_q_a[7]_clock_0, , , );
AB1_q_a[0] = AB1_q_a[7]_PORT_A_data_out_reg[7];

--AB1_q_a[1] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|q_a[1] at M4K_X17_Y7
AB1_q_a[7]_PORT_A_data_in = BUS(M3L22, M3L91, M3L41, M3L2, M2L12, M2L61, M2L11, M2L2);
AB1_q_a[7]_PORT_A_data_in_reg = DFFE(AB1_q_a[7]_PORT_A_data_in, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[7]_PORT_A_address_reg = DFFE(AB1_q_a[7]_PORT_A_address, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_write_enable = 70;
AB1_q_a[7]_PORT_A_write_enable_reg = DFFE(AB1_q_a[7]_PORT_A_write_enable, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_clock_0 = GLOBAL(CLK);
AB1_q_a[7]_PORT_A_data_out = MEMORY(AB1_q_a[7]_PORT_A_data_in_reg, , AB1_q_a[7]_PORT_A_address_reg, , AB1_q_a[7]_PORT_A_write_enable_reg, , , , AB1_q_a[7]_clock_0, , , , , );
AB1_q_a[7]_PORT_A_data_out_reg = DFFE(AB1_q_a[7]_PORT_A_data_out, AB1_q_a[7]_clock_0, , , );
AB1_q_a[1] = AB1_q_a[7]_PORT_A_data_out_reg[6];

--AB1_q_a[2] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|q_a[2] at M4K_X17_Y7
AB1_q_a[7]_PORT_A_data_in = BUS(M3L22, M3L91, M3L41, M3L2, M2L12, M2L61, M2L11, M2L2);
AB1_q_a[7]_PORT_A_data_in_reg = DFFE(AB1_q_a[7]_PORT_A_data_in, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[7]_PORT_A_address_reg = DFFE(AB1_q_a[7]_PORT_A_address, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_write_enable = 70;
AB1_q_a[7]_PORT_A_write_enable_reg = DFFE(AB1_q_a[7]_PORT_A_write_enable, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_clock_0 = GLOBAL(CLK);
AB1_q_a[7]_PORT_A_data_out = MEMORY(AB1_q_a[7]_PORT_A_data_in_reg, , AB1_q_a[7]_PORT_A_address_reg, , AB1_q_a[7]_PORT_A_write_enable_reg, , , , AB1_q_a[7]_clock_0, , , , , );
AB1_q_a[7]_PORT_A_data_out_reg = DFFE(AB1_q_a[7]_PORT_A_data_out, AB1_q_a[7]_clock_0, , , );
AB1_q_a[2] = AB1_q_a[7]_PORT_A_data_out_reg[5];

--AB1_q_a[3] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|q_a[3] at M4K_X17_Y7
AB1_q_a[7]_PORT_A_data_in = BUS(M3L22, M3L91, M3L41, M3L2, M2L12, M2L61, M2L11, M2L2);
AB1_q_a[7]_PORT_A_data_in_reg = DFFE(AB1_q_a[7]_PORT_A_data_in, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[7]_PORT_A_address_reg = DFFE(AB1_q_a[7]_PORT_A_address, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_write_enable = 70;
AB1_q_a[7]_PORT_A_write_enable_reg = DFFE(AB1_q_a[7]_PORT_A_write_enable, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_clock_0 = GLOBAL(CLK);
AB1_q_a[7]_PORT_A_data_out = MEMORY(AB1_q_a[7]_PORT_A_data_in_reg, , AB1_q_a[7]_PORT_A_address_reg, , AB1_q_a[7]_PORT_A_write_enable_reg, , , , AB1_q_a[7]_clock_0, , , , , );
AB1_q_a[7]_PORT_A_data_out_reg = DFFE(AB1_q_a[7]_PORT_A_data_out, AB1_q_a[7]_clock_0, , , );
AB1_q_a[3] = AB1_q_a[7]_PORT_A_data_out_reg[4];

--AB1_q_a[4] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|q_a[4] at M4K_X17_Y7
AB1_q_a[7]_PORT_A_data_in = BUS(M3L22, M3L91, M3L41, M3L2, M2L12, M2L61, M2L11, M2L2);
AB1_q_a[7]_PORT_A_data_in_reg = DFFE(AB1_q_a[7]_PORT_A_data_in, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[7]_PORT_A_address_reg = DFFE(AB1_q_a[7]_PORT_A_address, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_write_enable = 70;
AB1_q_a[7]_PORT_A_write_enable_reg = DFFE(AB1_q_a[7]_PORT_A_write_enable, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_clock_0 = GLOBAL(CLK);
AB1_q_a[7]_PORT_A_data_out = MEMORY(AB1_q_a[7]_PORT_A_data_in_reg, , AB1_q_a[7]_PORT_A_address_reg, , AB1_q_a[7]_PORT_A_write_enable_reg, , , , AB1_q_a[7]_clock_0, , , , , );
AB1_q_a[7]_PORT_A_data_out_reg = DFFE(AB1_q_a[7]_PORT_A_data_out, AB1_q_a[7]_clock_0, , , );
AB1_q_a[4] = AB1_q_a[7]_PORT_A_data_out_reg[3];

--AB1_q_a[5] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|q_a[5] at M4K_X17_Y7
AB1_q_a[7]_PORT_A_data_in = BUS(M3L22, M3L91, M3L41, M3L2, M2L12, M2L61, M2L11, M2L2);
AB1_q_a[7]_PORT_A_data_in_reg = DFFE(AB1_q_a[7]_PORT_A_data_in, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[7]_PORT_A_address_reg = DFFE(AB1_q_a[7]_PORT_A_address, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_write_enable = 70;
AB1_q_a[7]_PORT_A_write_enable_reg = DFFE(AB1_q_a[7]_PORT_A_write_enable, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_clock_0 = GLOBAL(CLK);
AB1_q_a[7]_PORT_A_data_out = MEMORY(AB1_q_a[7]_PORT_A_data_in_reg, , AB1_q_a[7]_PORT_A_address_reg, , AB1_q_a[7]_PORT_A_write_enable_reg, , , , AB1_q_a[7]_clock_0, , , , , );
AB1_q_a[7]_PORT_A_data_out_reg = DFFE(AB1_q_a[7]_PORT_A_data_out, AB1_q_a[7]_clock_0, , , );
AB1_q_a[5] = AB1_q_a[7]_PORT_A_data_out_reg[2];

--AB1_q_a[6] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|q_a[6] at M4K_X17_Y7
AB1_q_a[7]_PORT_A_data_in = BUS(M3L22, M3L91, M3L41, M3L2, M2L12, M2L61, M2L11, M2L2);
AB1_q_a[7]_PORT_A_data_in_reg = DFFE(AB1_q_a[7]_PORT_A_data_in, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[7]_PORT_A_address_reg = DFFE(AB1_q_a[7]_PORT_A_address, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_write_enable = 70;
AB1_q_a[7]_PORT_A_write_enable_reg = DFFE(AB1_q_a[7]_PORT_A_write_enable, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_clock_0 = GLOBAL(CLK);
AB1_q_a[7]_PORT_A_data_out = MEMORY(AB1_q_a[7]_PORT_A_data_in_reg, , AB1_q_a[7]_PORT_A_address_reg, , AB1_q_a[7]_PORT_A_write_enable_reg, , , , AB1_q_a[7]_clock_0, , , , , );
AB1_q_a[7]_PORT_A_data_out_reg = DFFE(AB1_q_a[7]_PORT_A_data_out, AB1_q_a[7]_clock_0, , , );
AB1_q_a[6] = AB1_q_a[7]_PORT_A_data_out_reg[1];


--U4L71 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~88 at LC_X15_Y6_N5
--operation mode is normal

B9_12_qfbk = B9_12;
U4L71 = U4L51 & U4L61 # !U4L51 & (U4L61 & B9_12_qfbk # !U4L61 & (AB1_q_a[7]));

--B9_12 is 8cpu:92|alu:62|74273b:11|12 at LC_X15_Y6_N5
--operation mode is normal

B9_12 = DFFEAS(U4L71, P1_22, VCC, , , Y3L2, , , VCC);


--U4L81 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~89 at LC_X19_Y8_N6
--operation mode is normal

U4L81 = U4L51 & (U4L71 & kdata[8] # !U4L71 & (Z1L82)) # !U4L51 & U4L71;


--U4L91 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~90 at LC_X15_Y6_N9
--operation mode is normal

B1_14_qfbk = B1_14;
U4L91 = J1L2 & B1_14_qfbk & B1_15;

--B1_14 is 74273b:2|14 at LC_X15_Y6_N9
--operation mode is normal

B1_14 = DFFEAS(U4L91, GLOBAL(40), CLRN, , , L1_q_a[5], , , VCC);


--Z1L52 is 8cpu:92|bi74670:67|74670c:32|121~11 at LC_X21_Y8_N8
--operation mode is normal

Z1L52 = 68 & (69 # Z1_66) # !68 & Z1_56 & !69;


--Z1L62 is 8cpu:92|bi74670:67|74670c:32|121~12 at LC_X21_Y8_N9
--operation mode is normal

Z1L62 = Z1L52 & (Z1_75 # !69) # !Z1L52 & Z1_65 & 69;


--U4L31 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result85w~16 at LC_X21_Y8_N2
--operation mode is normal

U4L31 = U4L51 & (Z1L62 # U4L61) # !U4L51 & (!U4L61 & AB1_q_a[6]);


--U4L41 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result85w~17 at LC_X22_Y6_N9
--operation mode is normal

B9_13_qfbk = B9_13;
U4L41 = U4L61 & (U4L31 & (kdata[7]) # !U4L31 & B9_13_qfbk) # !U4L61 & U4L31;

--B9_13 is 8cpu:92|alu:62|74273b:11|13 at LC_X22_Y6_N9
--operation mode is normal

B9_13 = DFFEAS(U4L41, P1_22, VCC, , , Y3L5, , , VCC);


--M3L61 is 8cpu:92|pc:65|74161:9|f74161:sub|95~0 at LC_X19_Y8_N3
--operation mode is arithmetic

M3L61 = M3_99 $ (M3L9 & M3_85);

--M3_95 is 8cpu:92|pc:65|74161:9|f74161:sub|95 at LC_X19_Y8_N3
--operation mode is arithmetic

M3_95_cout_0 = !M3_85 # !M3_99;
M3_95 = CARRY(M3_95_cout_0);

--M3L71 is 8cpu:92|pc:65|74161:9|f74161:sub|95~COUT1_2 at LC_X19_Y8_N3
--operation mode is arithmetic

M3L71_cout_1 = !M3L21 # !M3_99;
M3L71 = CARRY(M3L71_cout_1);


--Z1L32 is 8cpu:92|bi74670:67|74670c:32|112~11 at LC_X16_Y7_N5
--operation mode is normal

Z1L32 = 69 & (Z1_40 # 68) # !69 & Z1_51 & (!68);


--Z1L42 is 8cpu:92|bi74670:67|74670c:32|112~12 at LC_X16_Y7_N1
--operation mode is normal

Z1L42 = 68 & (Z1L32 & Z1_30 # !Z1L32 & (Z1_39)) # !68 & Z1L32;


--U4L11 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result73w~16 at LC_X15_Y6_N7
--operation mode is normal

B9_14_qfbk = B9_14;
U4L11 = U4L51 & (U4L61) # !U4L51 & (U4L61 & (B9_14_qfbk) # !U4L61 & AB1_q_a[5]);

--B9_14 is 8cpu:92|alu:62|74273b:11|14 at LC_X15_Y6_N7
--operation mode is normal

B9_14 = DFFEAS(U4L11, P1_22, VCC, , , Y3L8, , , VCC);


--U4L21 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result73w~17 at LC_X16_Y7_N6
--operation mode is normal

U4L21 = U4L11 & (kdata[6] # !U4L51) # !U4L11 & Z1L42 & (U4L51);


--M3L11 is 8cpu:92|pc:65|74161:9|f74161:sub|85~0 at LC_X19_Y8_N2
--operation mode is arithmetic

M3L11 = M3_87 $ (M3L9 & !M3_81);

--M3_85 is 8cpu:92|pc:65|74161:9|f74161:sub|85 at LC_X19_Y8_N2
--operation mode is arithmetic

M3_85_cout_0 = M3_87 & (!M3_81);
M3_85 = CARRY(M3_85_cout_0);

--M3L21 is 8cpu:92|pc:65|74161:9|f74161:sub|85~COUT1_2 at LC_X19_Y8_N2
--operation mode is arithmetic

M3L21_cout_1 = M3_87 & (!M3L5);
M3L21 = CARRY(M3L21_cout_1);


--Z1L12 is 8cpu:92|bi74670:67|74670c:32|107~11 at LC_X16_Y8_N4
--operation mode is normal

Z1L12 = 68 & (Z1_20 # 69) # !68 & (Z1_5 & !69);


--Z1L22 is 8cpu:92|bi74670:67|74670c:32|107~12 at LC_X16_Y8_N8
--operation mode is normal

Z1L22 = Z1L12 & (Z1_29 # !69) # !Z1L12 & Z1_19 & (69);


--U4L9 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result61w~16 at LC_X16_Y8_N5
--operation mode is normal

U4L9 = U4L61 & (U4L51) # !U4L61 & (U4L51 & Z1L22 # !U4L51 & (AB1_q_a[4]));


--U4L01 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result61w~17 at LC_X15_Y6_N4
--operation mode is normal

B9_15_qfbk = B9_15;
U4L01 = U4L9 & (kdata[5] # !U4L61) # !U4L9 & U4L61 & B9_15_qfbk;

--B9_15 is 8cpu:92|alu:62|74273b:11|15 at LC_X15_Y6_N4
--operation mode is normal

B9_15 = DFFEAS(U4L01, P1_22, VCC, , , Y3L11, , , VCC);


--M3L4 is 8cpu:92|pc:65|74161:9|f74161:sub|81~0 at LC_X19_Y8_N1
--operation mode is arithmetic

M3L4 = M3_9 $ (M3L7);

--M3_81 is 8cpu:92|pc:65|74161:9|f74161:sub|81 at LC_X19_Y8_N1
--operation mode is arithmetic

M3_81_cout_0 = !M3L7 # !M3_9;
M3_81 = CARRY(M3_81_cout_0);

--M3L5 is 8cpu:92|pc:65|74161:9|f74161:sub|81~COUT1 at LC_X19_Y8_N1
--operation mode is arithmetic

M3L5_cout_1 = !M3L8 # !M3_9;
M3L5 = CARRY(M3L5_cout_1);


--Z2L32 is 8cpu:92|bi74670:67|74670c:34|126~11 at LC_X16_Y7_N3
--operation mode is normal

Z2L32 = 69 & (Z2_86 # 68) # !69 & (Z2_95 & !68);


--Z2L42 is 8cpu:92|bi74670:67|74670c:34|126~12 at LC_X19_Y6_N8
--operation mode is normal

Z2L42 = 68 & (Z2L32 & (Z2_76) # !Z2L32 & Z2_85) # !68 & (Z2L32);


--U4L7 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result49w~16 at LC_X19_Y6_N2
--operation mode is normal

B9_16_qfbk = B9_16;
U4L7 = U4L61 & (B9_16_qfbk # U4L51) # !U4L61 & AB1_q_a[3] & (!U4L51);

--B9_16 is 8cpu:92|alu:62|74273b:11|16 at LC_X19_Y6_N2
--operation mode is normal

B9_16 = DFFEAS(U4L7, P1_22, VCC, , , Y3L51, , , VCC);


--U4L8 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result49w~17 at LC_X19_Y6_N0
--operation mode is normal

U4L8 = U4L7 & (kdata[4] # !U4L51) # !U4L7 & Z2L42 & (U4L51);


--M2L81 is 8cpu:92|pc:65|74161:8|f74161:sub|105~0 at LC_X20_Y7_N3
--operation mode is arithmetic

M2L81 = M2_110 $ (M2_95);

--M2_105 is 8cpu:92|pc:65|74161:8|f74161:sub|105 at LC_X20_Y7_N3
--operation mode is arithmetic

M2_105_cout_0 = !M2_95 # !M2_110;
M2_105 = CARRY(M2_105_cout_0);

--M2L91 is 8cpu:92|pc:65|74161:8|f74161:sub|105~COUT1_2 at LC_X20_Y7_N3
--operation mode is arithmetic

M2L91_cout_1 = !M2L41 # !M2_110;
M2L91 = CARRY(M2L91_cout_1);


--Z2L12 is 8cpu:92|bi74670:67|74670c:34|121~11 at LC_X20_Y6_N6
--operation mode is normal

Z2L12 = 69 & 68 # !69 & (68 & Z2_66 # !68 & (Z2_56));


--Z2L22 is 8cpu:92|bi74670:67|74670c:34|121~12 at LC_X20_Y6_N2
--operation mode is normal

Z2L22 = 69 & (Z2L12 & Z2_75 # !Z2L12 & (Z2_65)) # !69 & (Z2L12);


--U4L5 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result37w~16 at LC_X20_Y6_N1
--operation mode is normal

U4L5 = U4L61 & (U4L51) # !U4L61 & (U4L51 & Z2L22 # !U4L51 & (AB1_q_a[2]));


--U4L6 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result37w~17 at LC_X20_Y6_N0
--operation mode is normal

B9_17_qfbk = B9_17;
U4L6 = U4L61 & (U4L5 & kdata[3] # !U4L5 & (B9_17_qfbk)) # !U4L61 & (U4L5);

--B9_17 is 8cpu:92|alu:62|74273b:11|17 at LC_X20_Y6_N0
--operation mode is normal

B9_17 = DFFEAS(U4L6, P1_22, VCC, , , Y3L81, , , VCC);


--M2L31 is 8cpu:92|pc:65|74161:8|f74161:sub|95~0 at LC_X20_Y7_N2
--operation mode is arithmetic

M2L31 = M2_99 $ (!M2_85);

--M2_95 is 8cpu:92|pc:65|74161:8|f74161:sub|95 at LC_X20_Y7_N2
--operation mode is arithmetic

M2_95_cout_0 = M2_99 & (!M2_85);
M2_95 = CARRY(M2_95_cout_0);

--M2L41 is 8cpu:92|pc:65|74161:8|f74161:sub|95~COUT1_2 at LC_X20_Y7_N2
--operation mode is arithmetic

M2L41_cout_1 = M2_99 & (!M2L9);
M2L41 = CARRY(M2L41_cout_1);


--Z2L91 is 8cpu:92|bi74670:67|74670c:34|112~11 at LC_X21_Y7_N6
--operation mode is normal

Z2L91 = 68 & (69) # !68 & (69 & (Z2_40) # !69 & Z2_51);


--Z2L02 is 8cpu:92|bi74670:67|74670c:34|112~12 at LC_X21_Y7_N0
--operation mode is normal

Z2L02 = 68 & (Z2L91 & (Z2_30) # !Z2L91 & Z2_39) # !68 & (Z2L91);


--U4L3 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result25w~16 at LC_X19_Y6_N5
--operation mode is normal

B9_18_qfbk = B9_18;
U4L3 = U4L61 & (B9_18_qfbk # U4L51) # !U4L61 & AB1_q_a[1] & (!U4L51);

--B9_18 is 8cpu:92|alu:62|74273b:11|18 at LC_X19_Y6_N5
--operation mode is normal

B9_18 = DFFEAS(U4L3, P1_22, VCC, , , Y3L12, , , VCC);


--U4L4 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result25w~17 at LC_X21_Y7_N3
--operation mode is normal

U4L4 = U4L3 & (kdata[2] # !U4L51) # !U4L3 & U4L51 & (Z2L02);