mycpu.fit.eqn

Quantums 5.0开发环境

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--Y3L1 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~151 at LC_X22_Y6_N8
--operation mode is normal

Y3L1_carry_eqn = (!Y3L21 & Y3L3) # (Y3L21 & Y3L4);
Y3L1 = !Y3L1_carry_eqn;


--BB1_3 is sequence:103|74393b:25|3 at LC_X14_Y6_N3
--operation mode is normal

BB1_3_lut_out = !BB1_3;
BB1_3 = DFFEAS(BB1_3_lut_out, !GLOBAL(CLK), G1_11, , BB1_1, , , , );


--BB1_9 is sequence:103|74393b:25|9 at LC_X16_Y6_N2
--operation mode is normal

BB1_9_lut_out = !BB1_9;
BB1_9 = DFFEAS(BB1_9_lut_out, !GLOBAL(CLK), G1_11, , BB1_11, , , , );


--BB1_1 is sequence:103|74393b:25|1 at LC_X16_Y6_N9
--operation mode is normal

BB1_1_lut_out = !BB1_1;
BB1_1 = DFFEAS(BB1_1_lut_out, !GLOBAL(CLK), G1_11, , , , , , );


--BB1_5 is sequence:103|74393b:25|5 at LC_X14_Y6_N9
--operation mode is normal

BB1_5_lut_out = !BB1_5;
BB1_5 = DFFEAS(BB1_5_lut_out, !GLOBAL(CLK), G1_11, , BB1L4, , , , );


--J1L2 is sequence:103|33~19 at LC_X15_Y6_N8
--operation mode is normal

J1L2 = BB1_3 & !BB1_1 & BB1_9 & !BB1_5;


--J1_37 is sequence:103|37 at LC_X15_Y6_N6
--operation mode is normal

J1_37 = !BB1_3 & !BB1_1 & !BB1_9 & BB1_5;


--J1_35 is sequence:103|35 at LC_X19_Y6_N3
--operation mode is normal

J1_35 = BB1_5 & !BB1_3 & BB1_9 & !BB1_1;


--97 is 97 at LC_X19_Y10_N5
--operation mode is normal

B4_12_qfbk = B4_12;
97 = J1_35 & (B2_14 # B4_12_qfbk) # !CLRN;

--B4_12 is 74273b:21|12 at LC_X19_Y10_N5
--operation mode is normal

B4_12 = DFFEAS(97, GLOBAL(40), CLRN, , , L1_q_a[23], , , VCC);


--J1L1 is sequence:103|31~19 at LC_X19_Y6_N6
--operation mode is normal

J1L1 = BB1_5 & BB1_3 & !BB1_9 & !BB1_1;


--B6_12 is 8cpu:92|74273b:7|12 at LC_X19_Y8_N8
--operation mode is normal

B6_12_lut_out = M3L22;
B6_12 = DFFEAS(B6_12_lut_out, GLOBAL(H1_12), VCC, , , , , , );


--B6_13 is 8cpu:92|74273b:7|13 at LC_X19_Y8_N9
--operation mode is normal

B6_13_lut_out = M3L91;
B6_13 = DFFEAS(B6_13_lut_out, GLOBAL(H1_12), VCC, , , , , , );


--B6_14 is 8cpu:92|74273b:7|14 at LC_X15_Y8_N2
--operation mode is normal

B6_14_lut_out = M3L41;
B6_14 = DFFEAS(B6_14_lut_out, GLOBAL(H1_12), VCC, , , , , , );


--B6_15 is 8cpu:92|74273b:7|15 at LC_X16_Y8_N0
--operation mode is normal

B6_15_lut_out = M3L2;
B6_15 = DFFEAS(B6_15_lut_out, GLOBAL(H1_12), VCC, , , , , , );


--B6_16 is 8cpu:92|74273b:7|16 at LC_X25_Y7_N4
--operation mode is normal

B6_16_lut_out = GND;
B6_16 = DFFEAS(B6_16_lut_out, GLOBAL(H1_12), VCC, , , M2L12, , , VCC);


--B6_17 is 8cpu:92|74273b:7|17 at LC_X20_Y7_N8
--operation mode is normal

B6_17_lut_out = M2L61;
B6_17 = DFFEAS(B6_17_lut_out, GLOBAL(H1_12), VCC, , , , , , );


--B6_18 is 8cpu:92|74273b:7|18 at LC_X21_Y7_N8
--operation mode is normal

B6_18_lut_out = M2L11;
B6_18 = DFFEAS(B6_18_lut_out, GLOBAL(H1_12), VCC, , , , , , );


--B6_19 is 8cpu:92|74273b:7|19 at LC_X20_Y7_N7
--operation mode is normal

B6_19_lut_out = M2L2;
B6_19 = DFFEAS(B6_19_lut_out, GLOBAL(H1_12), VCC, , , , , , );


--B1_12 is 74273b:2|12 at LC_X15_Y6_N0
--operation mode is normal

B1_12_lut_out = L1_q_a[7];
B1_12 = DFFEAS(B1_12_lut_out, GLOBAL(40), CLRN, , , , , , );


--B2_15 is 74273b:3|15 at LC_X27_Y10_N0
--operation mode is normal

B2_15_lut_out = L1_q_a[12];
B2_15 = DFFEAS(B2_15_lut_out, GLOBAL(40), CLRN, , , , , , );


--B2_16 is 74273b:3|16 at LC_X27_Y10_N8
--operation mode is normal

B2_16_lut_out = GND;
B2_16 = DFFEAS(B2_16_lut_out, GLOBAL(40), CLRN, , , L1_q_a[11], , , VCC);


--B4_14 is 74273b:21|14 at LC_X27_Y10_N9
--operation mode is normal

B4_14_lut_out = L1_q_a[21];
B4_14 = DFFEAS(B4_14_lut_out, GLOBAL(40), CLRN, , , , , , );


--B4_15 is 74273b:21|15 at LC_X27_Y10_N2
--operation mode is normal

B4_15_lut_out = GND;
B4_15 = DFFEAS(B4_15_lut_out, GLOBAL(40), CLRN, , , L1_q_a[20], , , VCC);


--B4_16 is 74273b:21|16 at LC_X16_Y3_N2
--operation mode is normal

B4_16_lut_out = L1_q_a[19];
B4_16 = DFFEAS(B4_16_lut_out, GLOBAL(40), CLRN, , , , , , );


--B4_17 is 74273b:21|17 at LC_X16_Y3_N5
--operation mode is normal

B4_17_lut_out = GND;
B4_17 = DFFEAS(B4_17_lut_out, GLOBAL(40), CLRN, , , L1_q_a[18], , , VCC);


--B4_18 is 74273b:21|18 at LC_X16_Y3_N4
--operation mode is normal

B4_18_lut_out = L1_q_a[17];
B4_18 = DFFEAS(B4_18_lut_out, GLOBAL(40), CLRN, , , , , , );


--B4_19 is 74273b:21|19 at LC_X16_Y3_N6
--operation mode is normal

B4_19_lut_out = GND;
B4_19 = DFFEAS(B4_19_lut_out, GLOBAL(40), CLRN, , , L1_q_a[16], , , VCC);


--Y3L2 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~156 at LC_X22_Y6_N7
--operation mode is arithmetic

Y3L2_carry_eqn = (!Y3L21 & Y3L6) # (Y3L21 & Y3L7);
Y3L2 = B8_12 $ B7_12 $ Y3L2_carry_eqn;

--Y3L3 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~158 at LC_X22_Y6_N7
--operation mode is arithmetic

Y3L3_cout_0 = B8_12 & !B7_12 & !Y3L6 # !B8_12 & (!Y3L6 # !B7_12);
Y3L3 = CARRY(Y3L3_cout_0);

--Y3L4 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~158COUT1_202 at LC_X22_Y6_N7
--operation mode is arithmetic

Y3L4_cout_1 = B8_12 & !B7_12 & !Y3L7 # !B8_12 & (!Y3L7 # !B7_12);
Y3L4 = CARRY(Y3L4_cout_1);


--G1_11 is dcf:84|11 at LC_X14_Y7_N2
--operation mode is normal

G1_11_lut_out = VCC;
G1_11 = DFFEAS(G1_11_lut_out, VCC, !A1L31, , , VCC, !START, , );


--BB1_11 is sequence:103|74393b:25|11 at LC_X14_Y6_N2
--operation mode is normal

BB1_11 = BB1_3 & BB1_5 & BB1_1;


--BB1L4 is sequence:103|74393b:25|8~9 at LC_X14_Y6_N8
--operation mode is normal

BB1L4 = BB1_3 & (BB1_1);


--L1_q_a[23] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[23] at M4K_X17_Y9
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 18
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[23] = L1_q_a[23]_PORT_A_data_out_reg[0];

--L1_q_a[16] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[16] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[16] = L1_q_a[23]_PORT_A_data_out_reg[17];

--L1_q_a[17] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[17] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[17] = L1_q_a[23]_PORT_A_data_out_reg[16];

--L1_q_a[18] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[18] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[18] = L1_q_a[23]_PORT_A_data_out_reg[15];

--L1_q_a[19] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[19] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[19] = L1_q_a[23]_PORT_A_data_out_reg[14];

--L1_q_a[20] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[20] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[20] = L1_q_a[23]_PORT_A_data_out_reg[13];

--L1_q_a[22] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[22] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[22] = L1_q_a[23]_PORT_A_data_out_reg[12];

--L1_q_a[9] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[9] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[9] = L1_q_a[23]_PORT_A_data_out_reg[11];

--L1_q_a[10] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[10] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[10] = L1_q_a[23]_PORT_A_data_out_reg[10];

--L1_q_a[12] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[12] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[12] = L1_q_a[23]_PORT_A_data_out_reg[9];

--L1_q_a[14] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[14] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[14] = L1_q_a[23]_PORT_A_data_out_reg[8];

--L1_q_a[15] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[15] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[15] = L1_q_a[23]_PORT_A_data_out_reg[7];

--L1_q_a[1] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[1] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[1] = L1_q_a[23]_PORT_A_data_out_reg[6];

--L1_q_a[4] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[4] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[4] = L1_q_a[23]_PORT_A_data_out_reg[5];

--L1_q_a[5] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[5] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[5] = L1_q_a[23]_PORT_A_data_out_reg[4];

--L1_q_a[6] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[6] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[6] = L1_q_a[23]_PORT_A_data_out_reg[3];

--L1_q_a[7] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[7] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[7] = L1_q_a[23]_PORT_A_data_out_reg[2];

--L1_q_a[13] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[13] at M4K_X17_Y9
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = GLOBAL(CLK);
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[13] = L1_q_a[23]_PORT_A_data_out_reg[1];


--40 is 40 at LC_X7_Y9_N2
--operation mode is normal

40 = CLK & J1_37;