top.rpt

cpld 驱动sja1000

(unused)              0       0     0   5     FB7_15  87    I/O     I
cpu_data<6>           2       0     0   3     FB7_16  83    I/O     I/O
(unused)              0       0     0   5     FB7_17  88    I/O     I
(unused)              0       0     0   5     FB7_18        (b)     

Signals Used by Logic in Function Block
  1: can_en_data        5: can_ad<2>.PIN      8: can_ad<5>.PIN 
  2: can_rd             6: can_ad<3>.PIN      9: can_ad<6>.PIN 
  3: can_ad<0>.PIN      7: can_ad<4>.PIN     10: can_ad<7>.PIN 
  4: can_ad<1>.PIN    

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
cpu_data<0>          XXX..................................... 3
cpu_data<1>          XX.X.................................... 3
cpu_data<3>          XX...X.................................. 3
cpu_data<2>          XX..X................................... 3
cpu_data<5>          XX.....X................................ 3
cpu_data<7>          XX.......X.............................. 3
cpu_data<4>          XX....X................................. 3
cpu_data<6>          XX......X............................... 3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB8  ***********************************
Number of function block inputs used/remaining:               11/43
Number of signals used by logic mapping into function block:  11
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB8_1         (b)     
(unused)              0       0     0   5     FB8_2   91    I/O     I
(unused)              0       0     0   5     FB8_3   95    I/O     I
(unused)              0       0     0   5     FB8_4   97    I/O     I
(unused)              0       0     0   5     FB8_5   92    I/O     I
(unused)              0       0     0   5     FB8_6   93    I/O     I
(unused)              0       0     0   5     FB8_7         (b)     
(unused)              0       0     0   5     FB8_8   94    I/O     I
(unused)              0       0     0   5     FB8_9   96    I/O     I
can_ale               3       0     0   2     FB8_10  101   I/O     O
cf_reset              1       0     0   4     FB8_11  98    I/O     O
(unused)              0       0     0   5     FB8_12  100   I/O     I
cana_ncs              3       0     0   2     FB8_13  103   I/O     O
canb_ncs              3       0     0   2     FB8_14  102   I/O     O
can_rd                3       0     0   2     FB8_15  104   I/O     O
(unused)              0       0     0   5     FB8_16  107   I/O     
can_wr                4       0     0   1     FB8_17  105   I/O     O
(unused)              0       0     0   5     FB8_18        (b)     

Signals Used by Logic in Function Block
  1: can_state_FFd1     5: delay_can<0>                           9: cpu_noe 
  2: can_state_FFd2     6: delay_can<1>                          10: cpu_nwe 
  3: can_wr             7: delay_can<2>                          11: nreset_3828 
  4: cpu_addr23         8: delay_can<2>/delay_can<2>_RSTF__$INT 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
can_ale              XX..XXXX................................ 6
cf_reset             ..........X............................. 1
cana_ncs             XX.XXXXX................................ 7
canb_ncs             XX.XXXXX................................ 7
can_rd               XX.....XX............................... 4
can_wr               XXX.XXXX.X.............................. 8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********






















































can_ad_I(0) <= ((NOT can_en_addr AND cpu_addr(0))
	OR (cpu_data(8).PIN AND cpu_addr(0))
	OR (can_en_addr AND cpu_data(0).PIN AND NOT cpu_addr(0)));
can_ad(0) <= can_ad_I(0) when can_ad_OE(0) = '1' else 'Z';
can_ad_OE(0) <= can_ad_7_IOBUFE/can_ad_7_IOBUFE_TRST;


can_ad_I(1) <= ((NOT can_en_addr AND cpu_addr(1))
	OR (can_en_addr AND cpu_addr(0) AND cpu_data(9).PIN)
	OR (can_en_addr AND NOT cpu_addr(0) AND cpu_data(1).PIN));
can_ad(1) <= can_ad_I(1) when can_ad_OE(1) = '1' else 'Z';
can_ad_OE(1) <= can_ad_7_IOBUFE/can_ad_7_IOBUFE_TRST;


can_ad_I(2) <= ((NOT can_en_addr AND cpu_addr(2))
	OR (can_en_addr AND cpu_addr(0) AND cpu_data(10).PIN)
	OR (can_en_addr AND NOT cpu_addr(0) AND cpu_data(2).PIN));
can_ad(2) <= can_ad_I(2) when can_ad_OE(2) = '1' else 'Z';
can_ad_OE(2) <= can_ad_7_IOBUFE/can_ad_7_IOBUFE_TRST;


can_ad_I(3) <= ((NOT can_en_addr AND cpu_addr(3))
	OR (can_en_addr AND cpu_addr(0) AND cpu_data(11).PIN)
	OR (can_en_addr AND NOT cpu_addr(0) AND cpu_data(3).PIN));
can_ad(3) <= can_ad_I(3) when can_ad_OE(3) = '1' else 'Z';
can_ad_OE(3) <= can_ad_7_IOBUFE/can_ad_7_IOBUFE_TRST;


can_ad_I(4) <= ((NOT can_en_addr AND cpu_addr(4))
	OR (can_en_addr AND cpu_addr(0) AND cpu_data(12).PIN)
	OR (can_en_addr AND NOT cpu_addr(0) AND cpu_data(4).PIN));
can_ad(4) <= can_ad_I(4) when can_ad_OE(4) = '1' else 'Z';
can_ad_OE(4) <= can_ad_7_IOBUFE/can_ad_7_IOBUFE_TRST;


can_ad_I(5) <= ((NOT can_en_addr AND cpu_addr(5))
	OR (can_en_addr AND cpu_addr(0) AND cpu_data(13).PIN)
	OR (can_en_addr AND NOT cpu_addr(0) AND cpu_data(5).PIN));
can_ad(5) <= can_ad_I(5) when can_ad_OE(5) = '1' else 'Z';
can_ad_OE(5) <= can_ad_7_IOBUFE/can_ad_7_IOBUFE_TRST;


can_ad_I(6) <= ((NOT can_en_addr AND cpu_addr(6))
	OR (can_en_addr AND cpu_addr(0) AND cpu_data(14).PIN)
	OR (can_en_addr AND NOT cpu_addr(0) AND cpu_data(6).PIN));
can_ad(6) <= can_ad_I(6) when can_ad_OE(6) = '1' else 'Z';
can_ad_OE(6) <= can_ad_7_IOBUFE/can_ad_7_IOBUFE_TRST;


can_ad_I(7) <= ((NOT can_en_addr AND cpu_addr(7))
	OR (can_en_addr AND cpu_addr(0) AND cpu_data(15).PIN)
	OR (can_en_addr AND NOT cpu_addr(0) AND cpu_data(7).PIN));
can_ad(7) <= can_ad_I(7) when can_ad_OE(7) = '1' else 'Z';
can_ad_OE(7) <= can_ad_7_IOBUFE/can_ad_7_IOBUFE_TRST;


can_ad_7_IOBUFE/can_ad_7_IOBUFE_TRST <= ((NOT can_en_addr)
	OR (can_rd AND NOT can_en_data));

FDCPE_can_ale: FDCPE port map (can_ale,can_ale_D,NOT sysclk,NOT delay_can(2)/delay_can(2)_RSTF__$INT,'0',can_ale_CE);
can_ale_D <= (NOT delay_can(0) AND delay_can(1) AND NOT delay_can(2));
can_ale_CE <= (NOT can_state_FFd2 AND NOT can_state_FFd1);

FDCPE_can_dir: FDCPE port map (can_dir,cpu_noe,NOT sysclk,'0',NOT delay_can(2)/delay_can(2)_RSTF__$INT,can_dir_CE);
can_dir_CE <= (can_state_FFd2 AND NOT can_state_FFd1);

FDCPE_can_en_addr: FDCPE port map (can_en_addr,can_en_addr_D,NOT sysclk,'0',NOT delay_can(2)/delay_can(2)_RSTF__$INT);
can_en_addr_D <= ((can_en_addr AND can_state_FFd1)
	OR (can_state_FFd2 AND NOT can_state_FFd1));

FDCPE_can_en_data: FDCPE port map (can_en_data,'0',NOT sysclk,'0',NOT delay_can(2)/delay_can(2)_RSTF__$INT,can_en_data_CE);
can_en_data_CE <= (NOT can_state_FFd2 AND can_state_FFd1);


can_nreset <= nreset_3828;

FDCPE_can_rd: FDCPE port map (can_rd,cpu_noe,NOT sysclk,'0',NOT delay_can(2)/delay_can(2)_RSTF__$INT,can_rd_CE);
can_rd_CE <= (can_state_FFd2 AND NOT can_state_FFd1);

FDCPE_can_state_FFd1: FDCPE port map (can_state_FFd1,can_state_FFd1_D,NOT sysclk,NOT delay_can(2)/delay_can(2)_RSTF__$INT,'0');
can_state_FFd1_D <= (NOT can_state_FFd2 AND NOT can_state_FFd1);

FDCPE_can_state_FFd2: FDCPE port map (can_state_FFd2,can_state_FFd2_D,NOT sysclk,NOT delay_can(2)/delay_can(2)_RSTF__$INT,'0');
can_state_FFd2_D <= ((can_state_FFd2 AND can_state_FFd1)
	OR (can_state_FFd1 AND delay_can(0) AND delay_can(1) AND 
	NOT delay_can(2))
	OR (NOT can_state_FFd2 AND NOT can_state_FFd1 AND NOT delay_can(0) AND 
	delay_can(1) AND NOT delay_can(2)));

FTCPE_can_wr: FTCPE port map (can_wr,can_wr_T,NOT sysclk,'0',NOT delay_can(2)/delay_can(2)_RSTF__$INT);
can_wr_T <= ((can_wr AND can_state_FFd2 AND NOT can_state_FFd1 AND 
	NOT cpu_nwe)
	OR (NOT can_wr AND can_state_FFd2 AND NOT can_state_FFd1 AND 
	cpu_nwe)
	OR (NOT can_wr AND NOT can_state_FFd2 AND can_state_FFd1 AND 
	delay_can(0) AND delay_can(1) AND NOT delay_can(2)));

FDCPE_cana_ncs: FDCPE port map (cana_ncs,cpu_addr23,NOT sysclk,'0',NOT delay_can(2)/delay_can(2)_RSTF__$INT,cana_ncs_CE);
cana_ncs_CE <= (NOT can_state_FFd2 AND NOT can_state_FFd1 AND NOT delay_can(0) AND 
	delay_can(1) AND NOT delay_can(2));

FDCPE_canb_ncs: FDCPE port map (canb_ncs,NOT cpu_addr23,NOT sysclk,'0',NOT delay_can(2)/delay_can(2)_RSTF__$INT,canb_ncs_CE);
canb_ncs_CE <= (NOT can_state_FFd2 AND NOT can_state_FFd1 AND NOT delay_can(0) AND 
	delay_can(1) AND NOT delay_can(2));


cf_reset <= nreset_3828;


cpu_data_I(0) <= can_ad(0).PIN;
cpu_data(0) <= cpu_data_I(0) when cpu_data_OE(0) = '1' else 'Z';
cpu_data_OE(0) <= (NOT can_rd AND NOT can_en_data);


cpu_data_I(1) <= can_ad(1).PIN;
cpu_data(1) <= cpu_data_I(1) when cpu_data_OE(1) = '1' else 'Z';
cpu_data_OE(1) <= (NOT can_rd AND NOT can_en_data);


cpu_data_I(2) <= can_ad(2).PIN;
cpu_data(2) <= cpu_data_I(2) when cpu_data_OE(2) = '1' else 'Z';
cpu_data_OE(2) <= (NOT can_rd AND NOT can_en_data);


cpu_data_I(3) <= can_ad(3).PIN;