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cpldfit: version I.27 Xilinx Inc.
Fitter Report
Design Name: top Date: 9- 4-2006, 9:22PM
Device Used: XC95144XL-5-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
70 /144 ( 49%) 348 /720 ( 48%) 163/432 ( 38%) 37 /144 ( 26%) 53 /117 ( 45%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 7/18 22/54 81/90 0/15
FB2 8/18 22/54 68/90 0/15
FB3 4/18 22/54 16/90 2/15
FB4 15/18 20/54 36/90 6/15
FB5 10/18 22/54 76/90 5/14
FB6 12/18 34/54 38/90 12/13
FB7 8/18 10/54 16/90 8/15
FB8 6/18 11/54 17/90 6/15
----- ----- ----- -----
70/144 163/432 348/720 39/117
* - Resource is exhausted
** Global Control Resources **
Signal 'sysclk' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 13 13 | I/O : 52 109
Output : 15 15 | GCK/IO : 1 3
Bidirectional : 24 24 | GTS/IO : 0 4
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 53 53
** Power Data **
There are 70 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld:936 - The output buffer 'cpu_nwait_OBUF' is missing an input and
will be deleted.
WARNING:Cpld:1007 - Removing unused input(s) 'cpu_addr24'. The input(s) are
unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'cpu_ncs1'. The input(s) are
unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'cpu_ncs3'. The input(s) are
unused after optimization. Please verify functionality via simulation.
************************* Summary of Mapped Logic ************************
** 39 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
eth_nwe 1 1 FB3_15 50 I/O O STD FAST
eth_noe 1 1 FB3_17 51 I/O O STD FAST
can_ad<0> 4 5 FB4_1 118 I/O I/O STD FAST
cpu_data<11> 2 3 FB4_2 126 I/O I/O STD FAST
cpu_data<12> 2 3 FB4_5 128 I/O I/O STD FAST
cpu_data<13> 2 3 FB4_6 129 I/O I/O STD FAST
cpu_data<14> 2 3 FB4_8 130 I/O I/O STD FAST
cpu_data<15> 2 3 FB4_9 131 I/O I/O STD FAST
eth_clk 1 0 FB5_2 52 I/O O STD FAST RESET
eth_reset 1 1 FB5_5 53 I/O O STD FAST
test_led 7 14 FB5_6 54 I/O O STD FAST RESET
speaker 1 1 FB5_8 56 I/O O STD FAST
nreset_cpu 1 1 FB5_17 69 I/O O STD FAST
can_nreset 1 1 FB6_2 106 I/O O STD FAST
can_ad<6> 4 6 FB6_4 111 I/O I/O STD FAST
can_ad<7> 4 6 FB6_5 110 I/O I/O STD FAST
can_ad<5> 4 6 FB6_6 112 I/O I/O STD FAST
can_ad<4> 4 6 FB6_8 113 I/O I/O STD FAST
can_ad<2> 4 6 FB6_9 116 I/O I/O STD FAST
can_ad<3> 4 6 FB6_10 115 I/O I/O STD FAST
can_dir 3 4 FB6_12 120 I/O O STD FAST RESET
cpu_data<8> 2 3 FB6_14 121 I/O I/O STD FAST
cpu_data<9> 2 3 FB6_15 124 I/O I/O STD FAST
can_ad<1> 4 6 FB6_16 117 I/O I/O STD FAST
cpu_data<10> 2 3 FB6_17 125 I/O I/O STD FAST
cpu_data<0> 2 3 FB7_7 77 I/O I/O STD FAST
cpu_data<1> 2 3 FB7_8 78 I/O I/O STD FAST
cpu_data<3> 2 3 FB7_9 80 I/O I/O STD FAST
cpu_data<2> 2 3 FB7_10 79 I/O I/O STD FAST
cpu_data<5> 2 3 FB7_11 82 I/O I/O STD FAST
cpu_data<7> 2 3 FB7_12 85 I/O I/O STD FAST
cpu_data<4> 2 3 FB7_13 81 I/O I/O STD FAST
cpu_data<6> 2 3 FB7_16 83 I/O I/O STD FAST
can_ale 3 6 FB8_10 101 I/O O STD FAST RESET
cf_reset 1 1 FB8_11 98 I/O O STD FAST
cana_ncs 3 7 FB8_13 103 I/O O STD FAST RESET
canb_ncs 3 7 FB8_14 102 I/O O STD FAST RESET
can_rd 3 4 FB8_15 104 I/O O STD FAST RESET
can_wr 4 8 FB8_17 105 I/O O STD FAST SET
** 31 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
led_count<7> 15 22 FB1_2 STD RESET
led_count<11> 14 22 FB1_5 STD RESET
led_count<16> 13 22 FB1_8 STD RESET
led_count<8> 13 22 FB1_11 STD RESET
led_count<10> 12 22 FB1_14 STD RESET
led_count<18> 9 22 FB1_16 STD RESET
led_count<17> 5 22 FB1_18 STD RESET
led_count<21> 7 22 FB2_1 STD RESET
led_count<14> 7 21 FB2_6 STD RESET
led_count<0> 7 15 FB2_7 STD RESET
led_count<15> 7 22 FB2_8 STD RESET
led_count<20> 9 22 FB2_12 STD RESET
led_count<19> 9 22 FB2_14 STD RESET
led_count<1> 10 16 FB2_16 STD RESET
led_count<9> 12 21 FB2_18 STD RESET
led_count<13> 7 20 FB3_16 STD RESET
led_count<12> 7 19 FB3_18 STD RESET
delay_can<2>/delay_can<2>_RSTF__$INT 1 2 FB4_10 STD
delay_can<2> 2 4 FB4_11 STD RESET
can_state_FFd1 2 3 FB4_12 STD RESET
can_en_data 2 3 FB4_13 STD RESET
can_ad_7_IOBUFE/can_ad_7_IOBUFE_TRST 2 3 FB4_14 STD
delay_can<1> 3 6 FB4_15 STD RESET
delay_can<0> 3 6 FB4_16 STD RESET
can_en_addr 3 4 FB4_17 STD SET
can_state_FFd2 4 6 FB4_18 STD RESET
led_count<6> 15 21 FB5_1 STD RESET
led_count<2> 11 17 FB5_7 STD RESET
led_count<3> 12 18 FB5_10 STD RESET
led_count<4> 13 19 FB5_13 STD RESET
led_count<5> 14 20 FB5_16 STD RESET
** 14 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
sysclk FB3_2 32 GCK/I/O GCK
cpu_ncs5 FB5_13 70 I/O I
cpu_nwe FB5_14 61 I/O I
cpu_noe FB5_15 64 I/O I
cpu_addr23 FB7_15 87 I/O I
cpu_addr<7> FB7_17 88 I/O I
cpu_addr<6> FB8_2 91 I/O I
cpu_addr<2> FB8_3 95 I/O I
cpu_addr<0> FB8_4 97 I/O I
cpu_addr<5> FB8_5 92 I/O I
cpu_addr<4> FB8_6 93 I/O I
cpu_addr<3> FB8_8 94 I/O I
cpu_addr<1> FB8_9 96 I/O I
nreset_3828 FB8_12 100 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 22/32
Number of signals used by logic mapping into function block: 22
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 \/5 0 FB1_1 23 I/O (b)
led_count<7> 15 10<- 0 0 FB1_2 16 I/O (b)
(unused) 0 0 /\5 0 FB1_3 17 I/O (b)
(unused) 0 0 \/4 1 FB1_4 25 I/O (b)
led_count<11> 14 9<- 0 0 FB1_5 19 I/O (b)
(unused) 0 0 /\5 0 FB1_6 20 I/O (b)
(unused) 0 0 \/5 0 FB1_7 (b) (b)
led_count<16> 13 8<- 0 0 FB1_8 21 I/O (b)
(unused) 0 0 /\3 2 FB1_9 22 I/O (b)
(unused) 0 0 \/5 0 FB1_10 31 I/O (b)
led_count<8> 13 8<- 0 0 FB1_11 24 I/O (b)
(unused) 0 0 /\3 2 FB1_12 26 I/O (b)
(unused) 0 0 \/5 0 FB1_13 (b) (b)
led_count<10> 12 7<- 0 0 FB1_14 27 I/O (b)
(unused) 0 0 /\2 3 FB1_15 28 I/O (b)
led_count<18> 9 4<- 0 0 FB1_16 35 I/O (b)
(unused) 0 0 /\4 1 FB1_17 30 GCK/I/O (b)
led_count<17> 5 0 0 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: led_count<0> 9: led_count<17> 16: led_count<3>
2: led_count<10> 10: led_count<18> 17: led_count<4>
3: led_count<11> 11: led_count<19> 18: led_count<5>
4: led_count<12> 12: led_count<1> 19: led_count<6>
5: led_count<13> 13: led_count<20> 20: led_count<7>
6: led_count<14> 14: led_count<21> 21: led_count<8>
7: led_count<15> 15: led_count<2> 22: led_count<9>
8: led_count<16>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
led_count<7> XXXXXXXXXXXXXXXXXXXXXX.................. 22
led_count<11> XXXXXXXXXXXXXXXXXXXXXX.................. 22
led_count<16> XXXXXXXXXXXXXXXXXXXXXX.................. 22
led_count<8> XXXXXXXXXXXXXXXXXXXXXX.................. 22
led_count<10> XXXXXXXXXXXXXXXXXXXXXX.................. 22
led_count<18> XXXXXXXXXXXXXXXXXXXXXX.................. 22
led_count<17> XXXXXXXXXXXXXXXXXXXXXX.................. 22
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 22/32
Number of signals used by logic mapping into function block: 22
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
led_count<21> 7 4<- /\2 0 FB2_1 142 I/O (b)
(unused) 0 0 /\4 1 FB2_2 143 GSR/I/O (b)
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 4 I/O
(unused) 0 0 \/4 1 FB2_5 2 GTS/I/O (b)
led_count<14> 7 4<- \/2 0 FB2_6 3 GTS/I/O (b)
led_count<0> 7 2<- 0 0 FB2_7 (b) (b)
led_count<15> 7 2<- 0 0 FB2_8 5 GTS/I/O (b)
(unused) 0 0 /\2 3 FB2_9 6 GTS/I/O (b)
(unused) 0 0 0 5 FB2_10 7 I/O
(unused) 0 0 \/4 1 FB2_11 9 I/O (b)
led_count<20> 9 4<- 0 0 FB2_12 10 I/O (b)
(unused) 0 0 \/4 1 FB2_13 12 I/O (b)
led_count<19> 9 4<- 0 0 FB2_14 11 I/O (b)
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