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<span id="legend" class="pgRef"><h3 align="center">Legends</h3>
<table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td align="right"><form><input type="button" onclick="javascript:document.location.href='pinlegend.htm'" value="brief"></form></td></tr></table>
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<th width="20%">Acronym</th>
<th width="80%">Verbose Description</th>
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<td width="20%">聽CLK</td>
<td width="60%">聽Global Clock</td>
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<td width="20%">聽GCK0</td>
<td width="60%">聽Global clock zero</td>
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<td width="20%">聽GCK1</td>
<td width="60%">聽Global clock one</td>
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<td width="20%">聽GCK2</td>
<td width="60%">聽Global clock two</td>
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<td width="20%">聽GND</td>
<td width="60%">聽Dedicated Ground Pin</td>
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<td width="20%">聽GSR</td>
<td width="60%">聽Global set-reset</td>
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<td width="20%">聽GTS0</td>
<td width="60%">聽Global tristate zero (output enable)</td>
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<td width="20%">聽GTS1</td>
<td width="60%">聽Global tristate one (output enable)</td>
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<td width="20%">聽GTS2</td>
<td width="60%">聽Global tristate two (output enable)</td>
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<td width="20%">聽GTS3</td>
<td width="60%">聽Global tristate three (output enable)</td>
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<td width="20%">聽I/O</td>
<td width="60%">聽Input/Output</td>
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<td width="20%">聽INIT</td>
<td width="60%">聽Initial state</td>
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<td width="20%">聽ISP</td>
<td width="60%">聽The use of the JTAG port to program the chip while it is powered in a system.</td>
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<td width="20%">聽JTAG</td>
<td width="60%">聽IEEE Standard 1149 (JTAG) boundary-scan test standard.</td>
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<td width="20%">聽KPR</td>
<td width="60%">聽Unused I/O with weak keeper (leave unconnected)</td>
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<td width="20%">聽NC</td>
<td width="60%">聽Not Connected, unbonded pin</td>
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<td width="20%">聽PGND</td>
<td width="60%">聽Programmable ground pin</td>
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<td width="20%">聽PROHIBITED</td>
<td width="60%">聽User reserved pin</td>
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<td width="20%">聽R</td>
<td width="60%">聽Reset</td>
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<td width="20%">聽S</td>
<td width="60%">聽Set</td>
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<td width="20%">聽TCK</td>
<td width="60%">聽One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pull-up forces TCK to a high level if left unconnected.</td>
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<td width="20%">聽TDI</td>
<td width="60%">聽One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial input for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level if left unconnected.</td>
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<td width="20%">聽TDO</td>
<td width="60%">聽One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial output for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level when it is not driven from an external source.</td>
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<td width="20%">聽TIE</td>
<td width="60%">聽Unused I/O floating -- must tie to VCC, GND or other signal</td>
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<td width="20%">聽TMS</td>
<td width="60%">聽One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It directs the device through its Test Access Port controller states. An internal pull-up forces TDI to a high level when it is not driven from an external source. TMS also provides the optional test reset signal of IEEE Std 1149 or IEEE Std 1532.</td>
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<td width="20%">聽LVCMOS</td>
<td width="60%">聽Low Voltage Complementary Metal Oxide Semiconductor 3.3 Volts</td>
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<td width="20%">聽LVCMOS25</td>
<td width="60%">聽External I/O supply voltage for LVCMOS25</td>
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<td width="20%">聽LVCMOS33</td>
<td width="60%">聽External I/O supply voltage for LVCMOS33</td>
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<td width="20%">聽LVTTL</td>
<td width="60%">聽Low Voltage Transistor Transistor Logic 3.3Volts</td>
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<td width="20%">聽VCCIO</td>
<td width="60%">聽External power for Inputs/Outputs</td>
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<td width="20%">聽VCC</td>
<td width="60%">聽Dedicated Power Pin, Internal supply voltage for the device</td>
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<td width="20%">聽WPU</td>
<td width="60%">聽Unused I/O with Internal Weak Pull Up (leave unconnected)</td>
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