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📄 superheterodyne.mdl

📁 This is a superheterodyne reciever simulation, created in MATLAB - Simulink. The purpose is to study
💻 MDL
📖 第 1 页 / 共 5 页
字号:
	      N			      "12"
	      Wlo		      "2*pi*(580-4.5)"
	      Whi		      "2*pi*(580+4.5)"
	      Rp		      "2"
	      Rs		      "40"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Analog\nFilter Design1"
	      Ports		      [1, 1]
	      Position		      [85, 51, 125, 89]
	      SourceBlock	      "dsparch4/Analog\nFilter Design"
	      SourceType	      "Analog Filter Design"
	      method		      "Butterworth"
	      filttype		      "Lowpass"
	      N			      "15"
	      Wlo		      "2*pi*4.5"
	      Whi		      "2*pi*(90+0.5)"
	      Rp		      "2"
	      Rs		      "40"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "DSBSC AM\nModulator\nPassband"
	      Ports		      [1, 1]
	      Position		      [155, 48, 210, 92]
	      SourceBlock	      "commanapbnd2/DSBSC AM\nModulator\nPassband"
	      SourceType	      "DSBSC AM Modulator Passband"
	      ShowPortLabels	      "FromPortIcon"
	      SystemSampleTime	      "-1"
	      FunctionWithSeparateData off
	      RTWMemSecFuncInitTerm   "Inherit from model"
	      RTWMemSecFuncExecute    "Inherit from model"
	      RTWMemSecDataConstants  "Inherit from model"
	      RTWMemSecDataInternal   "Inherit from model"
	      RTWMemSecDataParameters "Inherit from model"
	      Fc		      "580"
	      Ph		      "0"
	    }
	    Block {
	      BlockType		      SignalGenerator
	      Name		      "Signal\nGenerator"
	      Ports		      [0, 1]
	      Position		      [35, 55, 65, 85]
	      Frequency		      "3"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [345, 63, 375, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Analog\nFilter Design1"
	      SrcPort		      1
	      DstBlock		      "DSBSC AM\nModulator\nPassband"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Analog\nFilter Design"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "DSBSC AM\nModulator\nPassband"
	      SrcPort		      1
	      DstBlock		      "Analog\nFilter Design"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Signal\nGenerator"
	      SrcPort		      1
	      DstBlock		      "Analog\nFilter Design1"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Canal7"
	  Ports			  [0, 1]
	  Position		  [40, 391, 90, 429]
	  MinAlgLoopOccurrences	  off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  System {
	    Name		    "Canal7"
	    Location		    [256, 79, 754, 379]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Reference
	      Name		      "Analog\nFilter Design"
	      Ports		      [1, 1]
	      Position		      [245, 48, 295, 92]
	      SourceBlock	      "dsparch4/Analog\nFilter Design"
	      SourceType	      "Analog Filter Design"
	      method		      "Butterworth"
	      filttype		      "Bandpass"
	      N			      "12"
	      Wlo		      "2*pi*(590-4.5)"
	      Whi		      "2*pi*(590+4.5)"
	      Rp		      "2"
	      Rs		      "40"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Analog\nFilter Design1"
	      Ports		      [1, 1]
	      Position		      [85, 51, 125, 89]
	      SourceBlock	      "dsparch4/Analog\nFilter Design"
	      SourceType	      "Analog Filter Design"
	      method		      "Butterworth"
	      filttype		      "Lowpass"
	      N			      "15"
	      Wlo		      "2*pi*4.5"
	      Whi		      "2*pi*(90+0.5)"
	      Rp		      "2"
	      Rs		      "40"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "DSBSC AM\nModulator\nPassband"
	      Ports		      [1, 1]
	      Position		      [155, 48, 210, 92]
	      SourceBlock	      "commanapbnd2/DSBSC AM\nModulator\nPassband"
	      SourceType	      "DSBSC AM Modulator Passband"
	      ShowPortLabels	      "FromPortIcon"
	      SystemSampleTime	      "-1"
	      FunctionWithSeparateData off
	      RTWMemSecFuncInitTerm   "Inherit from model"
	      RTWMemSecFuncExecute    "Inherit from model"
	      RTWMemSecDataConstants  "Inherit from model"
	      RTWMemSecDataInternal   "Inherit from model"
	      RTWMemSecDataParameters "Inherit from model"
	      Fc		      "590"
	      Ph		      "0"
	    }
	    Block {
	      BlockType		      SignalGenerator
	      Name		      "Signal\nGenerator"
	      Ports		      [0, 1]
	      Position		      [35, 55, 65, 85]
	      Frequency		      "3.5"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [345, 63, 375, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Signal\nGenerator"
	      SrcPort		      1
	      DstBlock		      "Analog\nFilter Design1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "DSBSC AM\nModulator\nPassband"
	      SrcPort		      1
	      DstBlock		      "Analog\nFilter Design"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Analog\nFilter Design"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Analog\nFilter Design1"
	      SrcPort		      1
	      DstBlock		      "DSBSC AM\nModulator\nPassband"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "DSB AM\nModulator\nPassband"
	  Ports			  [1, 1]
	  Position		  [345, 296, 390, 344]
	  SourceBlock		  "commanapbnd2/DSB AM\nModulator\nPassband"
	  SourceType		  "DSB AM Modulator Passband"
	  ShowPortLabels	  "FromPortIcon"
	  SystemSampleTime	  "-1"
	  FunctionWithSeparateData off
	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
	  Offset		  "0"
	  Fc			  "455"
	  Ph			  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "DSB AM\nModulator\nPassband1"
	  Ports			  [1, 1]
	  Position		  [345, 396, 390, 444]
	  SourceBlock		  "commanapbnd2/DSB AM\nModulator\nPassband"
	  SourceType		  "DSB AM Modulator Passband"
	  ShowPortLabels	  "FromPortIcon"
	  SystemSampleTime	  "-1"
	  FunctionWithSeparateData off
	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
	  Offset		  "0"
	  Fc			  "910+520+10*k"
	  Ph			  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "FTJ"
	  Ports			  [1, 1]
	  Position		  [295, 301, 325, 339]
	  SourceBlock		  "dsparch4/Analog\nFilter Design"
	  SourceType		  "Analog Filter Design"
	  method		  "Butterworth"
	  filttype		  "Lowpass"
	  N			  "15"
	  Wlo			  "2*pi*10"
	  Whi			  "2*pi*(90+0.5)"
	  Rp			  "2"
	  Rs			  "40"
	}
	Block {
	  BlockType		  Reference
	  Name			  "FTJ1"
	  Ports			  [1, 1]
	  Position		  [295, 401, 325, 439]
	  SourceBlock		  "dsparch4/Analog\nFilter Design"
	  SourceType		  "Analog Filter Design"
	  method		  "Butterworth"
	  filttype		  "Lowpass"
	  N			  "15"
	  Wlo			  "2*pi*10"
	  Whi			  "2*pi*(90+0.5)"
	  Rp			  "2"
	  Rs			  "40"
	}
	Block {
	  BlockType		  Gain
	  Name			  "Gain"
	  Position		  [410, 305, 440, 335]
	  Gain			  "10"
	  ParameterDataType	  "sfix(16)"
	  ParameterScaling	  "2^0"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Gain
	  Name			  "Gain1"
	  Position		  [410, 405, 440, 435]
	  Gain			  "10"
	  ParameterDataType	  "sfix(16)"
	  ParameterScaling	  "2^0"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  SignalGenerator
	  Name			  "Signal\nGenerator"
	  Ports			  [0, 1]
	  Position		  [245, 305, 275, 335]
	  WaveForm		  "random"
	  Frequency		  "0.5"
	}
	Block {
	  BlockType		  SignalGenerator
	  Name			  "Signal\nGenerator1"
	  Ports			  [0, 1]
	  Position		  [245, 405, 275, 435]
	  WaveForm		  "random"
	}
	Block {
	  BlockType		  Sum
	  Name			  "Sum"
	  Ports			  [7, 1]
	  Position		  [230, 16, 300, 114]
	  ShowName		  off
	  Inputs		  "+++++++"
	  CollapseMode		  "All dimensions"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Sum
	  Name			  "Sum1"
	  Ports			  [3, 1]
	  Position		  [495, 224, 525, 256]
	  ShowName		  off
	  Inputs		  "+++"
	  CollapseMode		  "All dimensions"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [615, 233, 645, 247]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Line {
	  SrcBlock		  "Canal1"
	  SrcPort		  1
	  Points		  [115, 0; 0, -15]
	  DstBlock		  "Sum"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Canal2"
	  SrcPort		  1
	  Points		  [105, 0; 0, -65]
	  DstBlock		  "Sum"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Canal3"
	  SrcPort		  1
	  Points		  [90, 0; 0, -110]
	  DstBlock		  "Sum"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Canal4"
	  SrcPort		  1
	  Points		  [120, 0]
	  DstBlock		  "Sum"
	  DstPort		  4
	}
	Line {
	  SrcBlock		  "Canal5"
	  SrcPort		  1
	  Points		  [90, 0; 0, -205]
	  DstBlock		  "Sum"
	  DstPort		  5
	}
	Line {
	  SrcBlock		  "Canal6"
	  SrcPort		  1
	  Points		  [105, 0; 0, -250]
	  DstBlock		  "Sum"
	  DstPort		  6
	}
	Line {
	  SrcBlock		  "Canal7"
	  SrcPort		  1
	  Points		  [115, 0; 0, -300]
	  DstBlock		  "Sum"
	  DstPort		  7
	}
	Line {
	  SrcBlock		  "Signal\nGenerator"
	  SrcPort		  1
	  DstBlock		  "FTJ"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sum1"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "DSB AM\nModulator\nPassband1"
	  SrcPort		  1
	  DstBlock		  "Gain1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "DSB AM\nModulator\nPassband"
	  SrcPort		  1
	  DstBlock		  "Gain"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Signal\nGenerator1"
	  SrcPort		  1
	  DstBlock		  "FTJ1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "FTJ1"
	  SrcPort		  1
	  DstBlock		  "DSB AM\nModulator\nPassband1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "FTJ"
	  SrcPort		  1
	  DstBlock		  "DSB AM\nModulator\nPassband"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sum"
	  SrcPort		  1
	  Points		  [0, 165]
	  DstBlock		  "Sum1"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      Reference
      Name		      "FTJ"
      Ports		      [1, 1]
      Position		      [615, 101, 655, 139]
      SourceBlock	      "dsparch4/Analog\nFilter Design"
      SourceType	    

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