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📄 superheterodyne.mdl

📁 This is a superheterodyne reciever simulation, created in MATLAB - Simulink. The purpose is to study
💻 MDL
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	      N			      "15"
	      Wlo		      "2*pi*4.5"
	      Whi		      "2*pi*(90+0.5)"
	      Rp		      "2"
	      Rs		      "40"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "DSBSC AM\nModulator\nPassband"
	      Ports		      [1, 1]
	      Position		      [155, 48, 210, 92]
	      SourceBlock	      "commanapbnd2/DSBSC AM\nModulator\nPassband"
	      SourceType	      "DSBSC AM Modulator Passband"
	      ShowPortLabels	      "FromPortIcon"
	      SystemSampleTime	      "-1"
	      FunctionWithSeparateData off
	      RTWMemSecFuncInitTerm   "Inherit from model"
	      RTWMemSecFuncExecute    "Inherit from model"
	      RTWMemSecDataConstants  "Inherit from model"
	      RTWMemSecDataInternal   "Inherit from model"
	      RTWMemSecDataParameters "Inherit from model"
	      Fc		      "540"
	      Ph		      "0"
	    }
	    Block {
	      BlockType		      SignalGenerator
	      Name		      "Signal\nGenerator"
	      Ports		      [0, 1]
	      Position		      [35, 55, 65, 85]
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [345, 63, 375, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Analog\nFilter Design1"
	      SrcPort		      1
	      DstBlock		      "DSBSC AM\nModulator\nPassband"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Analog\nFilter Design"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "DSBSC AM\nModulator\nPassband"
	      SrcPort		      1
	      DstBlock		      "Analog\nFilter Design"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Signal\nGenerator"
	      SrcPort		      1
	      DstBlock		      "Analog\nFilter Design1"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Canal3"
	  Ports			  [0, 1]
	  Position		  [40, 141, 90, 179]
	  MinAlgLoopOccurrences	  off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  System {
	    Name		    "Canal3"
	    Location		    [254, 82, 752, 382]
	    Open		    on
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Reference
	      Name		      "Analog\nFilter Design"
	      Ports		      [1, 1]
	      Position		      [245, 48, 295, 92]
	      SourceBlock	      "dsparch4/Analog\nFilter Design"
	      SourceType	      "Analog Filter Design"
	      method		      "Butterworth"
	      filttype		      "Bandpass"
	      N			      "12"
	      Wlo		      "2*pi*(550-4.5)"
	      Whi		      "2*pi*(550+4.5)"
	      Rp		      "2"
	      Rs		      "40"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Analog\nFilter Design1"
	      Ports		      [1, 1]
	      Position		      [85, 51, 125, 89]
	      SourceBlock	      "dsparch4/Analog\nFilter Design"
	      SourceType	      "Analog Filter Design"
	      method		      "Butterworth"
	      filttype		      "Lowpass"
	      N			      "15"
	      Wlo		      "2*pi*4.5"
	      Whi		      "2*pi*(90+0.5)"
	      Rp		      "2"
	      Rs		      "40"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "DSBSC AM\nModulator\nPassband"
	      Ports		      [1, 1]
	      Position		      [155, 48, 210, 92]
	      SourceBlock	      "commanapbnd2/DSBSC AM\nModulator\nPassband"
	      SourceType	      "DSBSC AM Modulator Passband"
	      ShowPortLabels	      "FromPortIcon"
	      SystemSampleTime	      "-1"
	      FunctionWithSeparateData off
	      RTWMemSecFuncInitTerm   "Inherit from model"
	      RTWMemSecFuncExecute    "Inherit from model"
	      RTWMemSecDataConstants  "Inherit from model"
	      RTWMemSecDataInternal   "Inherit from model"
	      RTWMemSecDataParameters "Inherit from model"
	      Fc		      "550"
	      Ph		      "0"
	    }
	    Block {
	      BlockType		      SignalGenerator
	      Name		      "Signal\nGenerator"
	      Ports		      [0, 1]
	      Position		      [35, 55, 65, 85]
	      Frequency		      "1.5"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [345, 63, 375, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Signal\nGenerator"
	      SrcPort		      1
	      DstBlock		      "Analog\nFilter Design1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "DSBSC AM\nModulator\nPassband"
	      SrcPort		      1
	      DstBlock		      "Analog\nFilter Design"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Analog\nFilter Design"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Analog\nFilter Design1"
	      SrcPort		      1
	      DstBlock		      "DSBSC AM\nModulator\nPassband"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Canal4"
	  Ports			  [0, 1]
	  Position		  [40, 211, 90, 249]
	  MinAlgLoopOccurrences	  off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  System {
	    Name		    "Canal4"
	    Location		    [252, 82, 750, 382]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Reference
	      Name		      "Analog\nFilter Design"
	      Ports		      [1, 1]
	      Position		      [245, 48, 295, 92]
	      SourceBlock	      "dsparch4/Analog\nFilter Design"
	      SourceType	      "Analog Filter Design"
	      method		      "Butterworth"
	      filttype		      "Bandpass"
	      N			      "12"
	      Wlo		      "2*pi*(560-4.5)"
	      Whi		      "2*pi*(560+4.5)"
	      Rp		      "2"
	      Rs		      "40"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Analog\nFilter Design1"
	      Ports		      [1, 1]
	      Position		      [80, 51, 120, 89]
	      SourceBlock	      "dsparch4/Analog\nFilter Design"
	      SourceType	      "Analog Filter Design"
	      method		      "Butterworth"
	      filttype		      "Lowpass"
	      N			      "15"
	      Wlo		      "2*pi*4.5"
	      Whi		      "2*pi*(90+0.5)"
	      Rp		      "2"
	      Rs		      "40"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "DSBSC AM\nModulator\nPassband"
	      Ports		      [1, 1]
	      Position		      [155, 48, 210, 92]
	      SourceBlock	      "commanapbnd2/DSBSC AM\nModulator\nPassband"
	      SourceType	      "DSBSC AM Modulator Passband"
	      ShowPortLabels	      "FromPortIcon"
	      SystemSampleTime	      "-1"
	      FunctionWithSeparateData off
	      RTWMemSecFuncInitTerm   "Inherit from model"
	      RTWMemSecFuncExecute    "Inherit from model"
	      RTWMemSecDataConstants  "Inherit from model"
	      RTWMemSecDataInternal   "Inherit from model"
	      RTWMemSecDataParameters "Inherit from model"
	      Fc		      "560"
	      Ph		      "0"
	    }
	    Block {
	      BlockType		      SignalGenerator
	      Name		      "Signal\nGenerator"
	      Ports		      [0, 1]
	      Position		      [35, 55, 65, 85]
	      Frequency		      "2"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [345, 63, 375, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Analog\nFilter Design1"
	      SrcPort		      1
	      DstBlock		      "DSBSC AM\nModulator\nPassband"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Analog\nFilter Design"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "DSBSC AM\nModulator\nPassband"
	      SrcPort		      1
	      DstBlock		      "Analog\nFilter Design"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Signal\nGenerator"
	      SrcPort		      1
	      DstBlock		      "Analog\nFilter Design1"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Canal5"
	  Ports			  [0, 1]
	  Position		  [40, 266, 90, 304]
	  MinAlgLoopOccurrences	  off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  System {
	    Name		    "Canal5"
	    Location		    [254, 79, 752, 379]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Reference
	      Name		      "Analog\nFilter Design"
	      Ports		      [1, 1]
	      Position		      [245, 48, 295, 92]
	      SourceBlock	      "dsparch4/Analog\nFilter Design"
	      SourceType	      "Analog Filter Design"
	      method		      "Butterworth"
	      filttype		      "Bandpass"
	      N			      "12"
	      Wlo		      "2*pi*(570-4.5)"
	      Whi		      "2*pi*(570+4.5)"
	      Rp		      "2"
	      Rs		      "40"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Analog\nFilter Design1"
	      Ports		      [1, 1]
	      Position		      [85, 51, 125, 89]
	      SourceBlock	      "dsparch4/Analog\nFilter Design"
	      SourceType	      "Analog Filter Design"
	      method		      "Butterworth"
	      filttype		      "Lowpass"
	      N			      "15"
	      Wlo		      "2*pi*4.5"
	      Whi		      "2*pi*(90+0.5)"
	      Rp		      "2"
	      Rs		      "40"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "DSBSC AM\nModulator\nPassband"
	      Ports		      [1, 1]
	      Position		      [155, 48, 210, 92]
	      SourceBlock	      "commanapbnd2/DSBSC AM\nModulator\nPassband"
	      SourceType	      "DSBSC AM Modulator Passband"
	      ShowPortLabels	      "FromPortIcon"
	      SystemSampleTime	      "-1"
	      FunctionWithSeparateData off
	      RTWMemSecFuncInitTerm   "Inherit from model"
	      RTWMemSecFuncExecute    "Inherit from model"
	      RTWMemSecDataConstants  "Inherit from model"
	      RTWMemSecDataInternal   "Inherit from model"
	      RTWMemSecDataParameters "Inherit from model"
	      Fc		      "570"
	      Ph		      "0"
	    }
	    Block {
	      BlockType		      SignalGenerator
	      Name		      "Signal\nGenerator"
	      Ports		      [0, 1]
	      Position		      [35, 55, 65, 85]
	      Frequency		      "2.5"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [345, 63, 375, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Signal\nGenerator"
	      SrcPort		      1
	      DstBlock		      "Analog\nFilter Design1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "DSBSC AM\nModulator\nPassband"
	      SrcPort		      1
	      DstBlock		      "Analog\nFilter Design"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Analog\nFilter Design"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Analog\nFilter Design1"
	      SrcPort		      1
	      DstBlock		      "DSBSC AM\nModulator\nPassband"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Canal6"
	  Ports			  [0, 1]
	  Position		  [40, 326, 90, 364]
	  MinAlgLoopOccurrences	  off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  System {
	    Name		    "Canal6"
	    Location		    [215, 167, 713, 467]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Reference
	      Name		      "Analog\nFilter Design"
	      Ports		      [1, 1]
	      Position		      [245, 48, 295, 92]
	      SourceBlock	      "dsparch4/Analog\nFilter Design"
	      SourceType	      "Analog Filter Design"
	      method		      "Butterworth"
	      filttype		      "Bandpass"
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